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authorJohnny Li <johnny_li@wistron.corp-partner.google.com>2020-10-08 09:11:21 +0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-10-30 15:04:04 +0000
commit8269692517808d44d0b9c8deecd9e9182892726f (patch)
treef3fee6b2269ff6d5976585a7cb29ba44ad620dde /src/mainboard/google
parent69c0b19ae1d17f52907d1d31ac45a48b6fe426a7 (diff)
mb/google/volteer/variants/volteer2: I2C5 trackpad bus freq 400 kHz
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C5 frequency is between 389-396kHz. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f Reviewed-on: https://review.coreboot.org/c/coreboot/+/46142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/volteer/variants/volteer2/overridetree.cb38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
index 2db1f087ef..3f666ac148 100644
--- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb
@@ -4,6 +4,44 @@ chip soc/intel/tigerlake
register "IomTypeCPortPadCfg[1]" = "0x090E000D"
register "DdiPort1Hpd" = "0"
register "DdiPort2Hpd" = "0"
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| GSPI1 | Fingerprint MCU |
+ #| I2C0 | Audio |
+ #| I2C1 | Touchscreen |
+ #| I2C2 | WLAN, SAR0 |
+ #| I2C3 | Camera, SAR1 |
+ #| I2C5 | Trackpad |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 163,
+ .scl_hcnt = 75,
+ .sda_hold = 36,
+ },
+ },
+ }"
register "HybridStorageMode" = "1"