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authorDuncan Laurie <dlaurie@chromium.org>2017-02-17 17:16:43 -0800
committerMartin Roth <martinroth@google.com>2017-02-19 21:39:02 +0100
commit25c7d9342b8bdee61710a516440e4b9c4b83fb09 (patch)
tree2700558a829fd4b7a8f1cba15c6c0e21b69bbc27 /src/mainboard/google
parentc9db384ea47b8b705ddeaf0319fd53b5c513f423 (diff)
soc/intel/skylake: Disable s0ix if not enabled in devicetree
There is an enable_s0ix config option in the devicetree that should be used to disable it when not set: - do not export C8/C9/C10 C-states in _CST - do not enable SLP_S0 in FSP BUG=chrome-os-partner:58666 TEST=test on eve board to ensure that OS only sees 3 ACPI C-states instead of 6 and that it no longer attempts to enter C10 Change-Id: I90e4dc776d1d17d0b700cda63c8476786cd2e4ff Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18394 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google')
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