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authorAbhay Kumar <abhay.kumar@intel.com>2016-06-27 10:46:48 -0700
committerAaron Durbin <adurbin@chromium.org>2016-07-01 03:52:57 +0200
commitcc37c85ab4edb0c5d3d0c3e82865b65e0f469875 (patch)
tree7a0b952f58131b2fc0ecc96b68a4c2edf2a6f9fa /src/mainboard/google
parentaf9f35a2ced060450f61eab2e62936b857bcd077 (diff)
mainboard/google/reef: Configure DDI0, DDI1 HPD GPIO lines
Configure GPIO_199 and GPIO_200 as NF2 to work as HPD. Change-Id: If3aa6b75ed22c221cfbedaecf16035cdd9939387 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/15447 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/reef/gpio.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h
index b41f5f9b65..bd491b49ff 100644
--- a/src/mainboard/google/reef/gpio.h
+++ b/src/mainboard/google/reef/gpio.h
@@ -178,8 +178,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1), /* PNL1_BKLTCTL */
/* Hot plug detect. */
- PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF1), /* HV_DDI1_HPD */
- PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF1), /* HV_DDI0_HPD */
+ PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */
+ PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */
/* MDSI signals -- unused */
PAD_CFG_GPI(GPIO_201, UP_20K, DEEP), /* MDSI_A_TE */