src: Remove unneeded whitespace

Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

15 files changed, 45 insertions, 45 deletions

diff --git a/src/mainboard/google/cyan/variants/banon/gpio.c b/src/mainboard/google/cyan/variants/banon/gpio.c
index 92ef836c0d..f9e4e3e362 100644
--- a/src/mainboard/google/cyan/variants/banon/gpio.c
+++ b/src/mainboard/google/cyan/variants/banon/gpio.c
@@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
 	GPIO_NC, /* 69 MMC1_RCLK */
 	Native_M1, /* 75  GPO USB_OC1_B */
 	Native_M1, /* 76  PMU_RESETBUTTON_B */
-	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
 	/* GPIO_ALERT 77   */
 	GPIO_NC, /* 78  SDMMC3_PWR_EN_B */
 	GPIO_NC, /* 79  GPI ILB_SERIRQ */
@@ -127,9 +127,9 @@ static const struct soc_gpio_map  gpsw_gpio_map[] = {
 	/* 76 GPI SATA_GP1 */
 	GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
 	GPIO_NC, /* 80 SATA_GP3 */
-	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
-	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
 	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
 	Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -156,7 +156,7 @@ static const struct soc_gpio_map  gpn_gpio_map[] = {
 	GPIO_NC, /* 06 GPIO_DFX8 */
 	GPIO_NC, /* 07 GPIO_DFX2 */
 	GPIO_NC, /* 08 GPIO_DFX6 */
-	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
 	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
 	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
 	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/celes/gpio.c b/src/mainboard/google/cyan/variants/celes/gpio.c
index d011428c3a..b4d8b1e280 100644
--- a/src/mainboard/google/cyan/variants/celes/gpio.c
+++ b/src/mainboard/google/cyan/variants/celes/gpio.c
@@ -66,13 +66,13 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
 	GPIO_NC, /* 69 MMC1_RCLK */
 	Native_M1, /* 75  GPO USB_OC1_B */
 	Native_M1, /* 76  PMU_RESETBUTTON_B */
-	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
 	/* GPIO_ALERT 77   */
 	Native_M1, /* 78  SDMMC3_PWR_EN_B */
 	GPIO_NC, /* 79  GPI ILB_SERIRQ */
 	Native_M1, /* 80  USB_OC0_B */
 	GPI(trig_edge_both, L1, P_20K_H, non_maskable,
-				en_edge_detect, NA , NA),
+				en_edge_detect, NA, NA),
 	/* 81  SDMMC3_CD_B */
 	GPIO_NC,  /* 82  spkr	 assumed gpio number */
 	Native_M1, /* 83 SUSPWRDNACK */
@@ -132,7 +132,7 @@ static const struct soc_gpio_map  gpsw_gpio_map[] = {
 	GPIO_NC, /* 78 SATA_GP2 */
 	GPIO_NC, /* 79 MF_SMB_ALERTB */
 	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
-	GPIO_NC, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	GPIO_NC, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	GPIO_NC, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
 	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
 	Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -159,7 +159,7 @@ static const struct soc_gpio_map  gpn_gpio_map[] = {
 	GPIO_NC, /* 06 GPIO_DFX8 */
 	GPIO_NC, /* 07 GPIO_DFX2 */
 	GPIO_NC, /* 08 GPIO_DFX6 */
-	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
 	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
 	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
 	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c
index bf869fec23..4cdfcdf18c 100644
--- a/src/mainboard/google/cyan/variants/cyan/gpio.c
+++ b/src/mainboard/google/cyan/variants/cyan/gpio.c
@@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
 	GPIO_NC, /* 69 MMC1_RCLK */
 	Native_M1, /* 75  GPO USB_OC1_B */
 	Native_M1, /* 76  PMU_RESETBUTTON_B */
-	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
 	/* GPIO_ALERT 77   */
 	Native_M1, /* 78  SDMMC3_PWR_EN_B */
 	GPIO_NC, /* 79  GPI ILB_SERIRQ */
@@ -130,7 +130,7 @@ static const struct soc_gpio_map  gpsw_gpio_map[] = {
 	GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */
 	Native_M1, /* 79 MF_SMB_ALERTB */
 	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
-	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
 	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
 	Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -159,7 +159,7 @@ static const struct soc_gpio_map  gpn_gpio_map[] = {
 	GPIO_NC, /* 06 GPIO_DFX8 */
 	GPIO_NC, /* 07 GPIO_DFX2 */
 	GPIO_NC, /* 08 GPIO_DFX6 */
-	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
 	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
 	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
 	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c
index d9d2648e37..2010ac5172 100644
--- a/src/mainboard/google/cyan/variants/edgar/gpio.c
+++ b/src/mainboard/google/cyan/variants/edgar/gpio.c
@@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
 	GPIO_NC, /* 69 MMC1_RCLK */
 	Native_M1, /* 75  GPO USB_OC1_B */
 	Native_M1, /* 76  PMU_RESETBUTTON_B */
-	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
 	/* GPIO_ALERT 77   */
 	Native_M1, /* 78  SDMMC3_PWR_EN_B */
 	GPIO_NC, /* 79  GPI ILB_SERIRQ */
@@ -129,7 +129,7 @@ static const struct soc_gpio_map  gpsw_gpio_map[] = {
 	GPIO_NC, /* 78 SATA_GP2 */
 	Native_M1, /* 79 MF_SMB_ALERTB */
 	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
-	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
 	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
 	GPIO_INPUT_PU_20K, /* 90 PCIE_CLKREQ0B */
@@ -156,7 +156,7 @@ static const struct soc_gpio_map  gpn_gpio_map[] = {
 	GPIO_NC, /* 06 GPIO_DFX8 */
 	GPIO_NC, /* 07 GPIO_DFX2 */
 	GPIO_NC, /* 08 GPIO_DFX6 */
-	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
 	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
 	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
 	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/kefka/gpio.c b/src/mainboard/google/cyan/variants/kefka/gpio.c
index 76549ba458..d628658228 100644
--- a/src/mainboard/google/cyan/variants/kefka/gpio.c
+++ b/src/mainboard/google/cyan/variants/kefka/gpio.c
@@ -67,7 +67,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
 	GPIO_NC, /* 69 MMC1_RCLK */
 	Native_M1, /* 75  GPO USB_OC1_B */
 	Native_M1, /* 76  PMU_RESETBUTTON_B */
-	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
 	/* GPIO_ALERT 77   */
 	Native_M1, /* 78  SDMMC3_PWR_EN_B */
 	GPIO_NC, /* 79  GPI ILB_SERIRQ */
@@ -129,7 +129,7 @@ static const struct soc_gpio_map  gpsw_gpio_map[] = {
 	GPIO_NC, /* 78 SATA_GP2 */
 	Native_M1, /* 79 MF_SMB_ALERTB */
 	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
-	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
 	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
 	GPIO_NC, /* 90 PCIE_CLKREQ0B */
@@ -156,7 +156,7 @@ static const struct soc_gpio_map  gpn_gpio_map[] = {
 	GPIO_NC, /* 06 GPIO_DFX8 */
 	GPIO_NC, /* 07 GPIO_DFX2 */
 	GPIO_NC, /* 08 GPIO_DFX6 */
-	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
 	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
 	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
 	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c
index 1a9e5404ef..7b9b5af83d 100644
--- a/src/mainboard/google/cyan/variants/reks/gpio.c
+++ b/src/mainboard/google/cyan/variants/reks/gpio.c
@@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
 	GPIO_NC, /* 69 MMC1_RCLK */
 	Native_M1, /* 75  GPO USB_OC1_B */
 	Native_M1, /* 76  PMU_RESETBUTTON_B */
-	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
 	/* GPIO_ALERT 77   */
 	Native_M1, /* 78  SDMMC3_PWR_EN_B */
 	GPIO_NC, /* 79  GPI ILB_SERIRQ */
@@ -129,9 +129,9 @@ static const struct soc_gpio_map  gpsw_gpio_map[] = {
 	/* 76 GPI SATA_GP1 */
 	GPIO_INPUT_PU_20K, /* 77 SATA_LEDN-> EC_IN_RW */
 	GPIO_NC, /* 80 SATA_GP3 */
-	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
-	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
 	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
 	Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -158,7 +158,7 @@ static const struct soc_gpio_map  gpn_gpio_map[] = {
 	GPIO_NC, /* 06 GPIO_DFX8 */
 	GPIO_NC, /* 07 GPIO_DFX2 */
 	GPIO_NC, /* 08 GPIO_DFX6 */
-	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
 	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
 	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
 	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/relm/gpio.c b/src/mainboard/google/cyan/variants/relm/gpio.c
index 6c1dbdced8..95c130073a 100644
--- a/src/mainboard/google/cyan/variants/relm/gpio.c
+++ b/src/mainboard/google/cyan/variants/relm/gpio.c
@@ -67,7 +67,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
 	GPIO_NC, /* 69 MMC1_RCLK */
 	Native_M1, /* 75  GPO USB_OC1_B */
 	Native_M1, /* 76  PMU_RESETBUTTON_B */
-	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
 	/* GPIO_ALERT 77   */
 	Native_M1, /* 78  SDMMC3_PWR_EN_B */
 	GPIO_NC, /* 79  GPI ILB_SERIRQ */
@@ -130,9 +130,9 @@ static const struct soc_gpio_map  gpsw_gpio_map[] = {
 	/* 76 GPI SATA_GP1 */
 	GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
 	GPIO_NC, /* 80 SATA_GP3 */
-	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
-	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
 	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
 	Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -159,7 +159,7 @@ static const struct soc_gpio_map  gpn_gpio_map[] = {
 	GPIO_NC, /* 06 GPIO_DFX8 */
 	GPIO_NC, /* 07 GPIO_DFX2 */
 	GPIO_NC, /* 08 GPIO_DFX6 */
-	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
 	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
 	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
 	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/setzer/gpio.c b/src/mainboard/google/cyan/variants/setzer/gpio.c
index df1bff1cef..1307f7ded6 100644
--- a/src/mainboard/google/cyan/variants/setzer/gpio.c
+++ b/src/mainboard/google/cyan/variants/setzer/gpio.c
@@ -67,7 +67,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
 	GPIO_NC, /* 69 MMC1_RCLK */
 	Native_M1, /* 75  GPO USB_OC1_B */
 	Native_M1, /* 76  PMU_RESETBUTTON_B */
-	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
 	/* GPIO_ALERT 77   */
 	Native_M1, /* 78  SDMMC3_PWR_EN_B */
 	GPIO_NC, /* 79  GPI ILB_SERIRQ */
@@ -128,9 +128,9 @@ static const struct soc_gpio_map  gpsw_gpio_map[] = {
 	/* 76 GPI SATA_GP1 */
 	GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
 	GPIO_NC, /* 78 SATA_GP2 */
-	Native_M1, /* 79 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 79 NFC_DEV_WAKE, MF_SMB_CLK */
 	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID3 */
-	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
 	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
 	GPIO_NC, /* 90 PCIE_CLKREQ0B */
@@ -157,7 +157,7 @@ static const struct soc_gpio_map  gpn_gpio_map[] = {
 	GPIO_NC, /* 06 GPIO_DFX8 */
 	GPIO_NC, /* 07 GPIO_DFX2 */
 	GPIO_NC, /* 08 GPIO_DFX6 */
-	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
 	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
 	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
 	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c
index 8328eddfec..b4feebff16 100644
--- a/src/mainboard/google/cyan/variants/terra/gpio.c
+++ b/src/mainboard/google/cyan/variants/terra/gpio.c
@@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
 	GPIO_NC, /* 69 MMC1_RCLK */
 	Native_M1, /* 75  GPO USB_OC1_B */
 	Native_M1, /* 76  PMU_RESETBUTTON_B */
-	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
 	/* GPIO_ALERT 77   */
 	Native_M1, /* 78  SDMMC3_PWR_EN_B */
 	GPIO_NC, /* 79  GPI ILB_SERIRQ */
@@ -128,7 +128,7 @@ static const struct soc_gpio_map  gpsw_gpio_map[] = {
 	GPIO_NC, /* 78 SATA_GP2 */
 	GPIO_NC, /* 79 MF_SMB_ALERTB */
 	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
-	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
 	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
 	Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -155,7 +155,7 @@ static const struct soc_gpio_map  gpn_gpio_map[] = {
 	GPIO_NC, /* 06 GPIO_DFX8 */
 	GPIO_NC, /* 07 GPIO_DFX2 */
 	GPIO_NC, /* 08 GPIO_DFX6 */
-	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
 	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
 	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
 	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/ultima/gpio.c b/src/mainboard/google/cyan/variants/ultima/gpio.c
index c6875b4ef2..43f1099a54 100644
--- a/src/mainboard/google/cyan/variants/ultima/gpio.c
+++ b/src/mainboard/google/cyan/variants/ultima/gpio.c
@@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
 	GPIO_NC, /* 69 MMC1_RCLK */
 	Native_M1, /* 75  GPO USB_OC1_B */
 	Native_M1, /* 76  PMU_RESETBUTTON_B */
-	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
 	/* GPIO_ALERT 77   */
 	Native_M1, /* 78  SDMMC3_PWR_EN_B */
 	GPIO_NC, /* 79  GPI ILB_SERIRQ */
@@ -129,9 +129,9 @@ static const struct soc_gpio_map  gpsw_gpio_map[] = {
 	/* 76 GPI SATA_GP1 */
 	GPIO_INPUT_PU_20K, /* 77 SATA_LEDN-> EC_IN_RW */
 	GPIO_NC, /* 80 SATA_GP3 */
-	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
-	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
 	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
 	Native_M1, /* 90 PCIE_CLKREQ0B */
@@ -158,7 +158,7 @@ static const struct soc_gpio_map  gpn_gpio_map[] = {
 	GPIO_NC, /* 06 GPIO_DFX8 */
 	GPIO_NC, /* 07 GPIO_DFX2 */
 	GPIO_NC, /* 08 GPIO_DFX6 */
-	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
 	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
 	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
 	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/cyan/variants/wizpig/gpio.c b/src/mainboard/google/cyan/variants/wizpig/gpio.c
index 361143932c..3d3b27359e 100644
--- a/src/mainboard/google/cyan/variants/wizpig/gpio.c
+++ b/src/mainboard/google/cyan/variants/wizpig/gpio.c
@@ -66,7 +66,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
 	GPIO_NC, /* 69 MMC1_RCLK */
 	Native_M1, /* 75  GPO USB_OC1_B */
 	Native_M1, /* 76  PMU_RESETBUTTON_B */
-	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),
+	GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA, NA),
 	/* GPIO_ALERT 77   */
 	Native_M1, /* 78  SDMMC3_PWR_EN_B */
 	GPIO_NC, /* 79  GPI ILB_SERIRQ */
@@ -128,9 +128,9 @@ static const struct soc_gpio_map  gpsw_gpio_map[] = {
 	GPIO_NC, /* 76 GPI SATA_GP1 */
 	GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */
 	GPIO_NC, /* 78 SATA_GP2 */
-	Native_M1, /* 79 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 79 NFC_DEV_WAKE, MF_SMB_CLK */
 	GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */
-	Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */
+	Native_M1, /* 81 NFC_DEV_WAKE, MF_SMB_CLK */
 	Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */
 	/* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */
 	GPIO_NC, /* 90 PCIE_CLKREQ0B */
@@ -157,7 +157,7 @@ static const struct soc_gpio_map  gpn_gpio_map[] = {
 	GPIO_NC, /* 06 GPIO_DFX8 */
 	GPIO_NC, /* 07 GPIO_DFX2 */
 	GPIO_NC, /* 08 GPIO_DFX6 */
-	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,
+	GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data,
 	UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */
 	GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
 	GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c
index 6f8ff0f19c..975eea5819 100644
--- a/src/mainboard/google/eve/romstage.c
+++ b/src/mainboard/google/eve/romstage.c
@@ -27,7 +27,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
-		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
 		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
 		  { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
 		    0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c
index 297b149b4b..4fe88ef7c8 100644
--- a/src/mainboard/google/glados/variants/lars/variant.c
+++ b/src/mainboard/google/glados/variants/lars/variant.c
@@ -33,9 +33,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
-		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
 		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
-		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
 		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
 	/* DQS CPU<>DRAM map */
 	const u8 dqs_map[2][8] = {
diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c
index aaa8ae7d0b..5b2985a7c2 100644
--- a/src/mainboard/google/gru/boardid.c
+++ b/src/mainboard/google/gru/boardid.c
@@ -65,7 +65,7 @@ static uint32_t get_index(uint32_t channel, int *cached_id)
 		}
 	}
 
-	die("Read impossible value ( > 1023) from 10-bit ADC!");
+	die("Read impossible value (> 1023) from 10-bit ADC!");
 }
 
 uint32_t board_id(void)
diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c
index 8b8000cb98..8bd758b958 100644
--- a/src/mainboard/google/link/i915.c
+++ b/src/mainboard/google/link/i915.c
@@ -295,7 +295,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 	index = run(index);
 	auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8;
 	auxout[1] = 0x0a840000;
-	/*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/
+	/*(DP_LINK_BW_2_7 &0xa)|0x0000840a*/
 	auxout[2] = 0x00000000;
 	auxout[3] = 0x01000000;
 	intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0);