diff options
| author | Martin Roth <martinroth@chromium.org> | 2020-12-02 16:37:58 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-03 23:44:28 +0000 |
| commit | 6a62cc85e61da5282611c2bee5ac3a54580f0113 (patch) | |
| tree | fda57c0c88be089d805c9978b034b2865c6dcd90 /src/mainboard/google | |
| parent | 361a5c095262adc139f0d7504fb25e1215eebc8f (diff) | |
mb/google/zork: Set S0IX_SLP_L high in S0, low in S3
This is used as a signal to show the system state. It hadn't been used
up to this point as we're not currently using S0i3, but the fingerprint
sensor will use it to go into a low power mode, so set it appropriately
on Trembyle. Dalboz devices don't use the FPMCU, but set there as well
so that the state matches.
BUG=b:174695987
TEST=Verify GPIO state in S0 and S3 with the EC
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibc725905909830d44f77c2498a26edf6d7a3dc05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48255
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Vincent Palatin <vpalatin@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c | 6 | ||||
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c | 6 |
2 files changed, 8 insertions, 4 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 884862d3dd..a528827879 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -30,8 +30,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), - /* S0iX SLP - (unused - goes to EC */ - PAD_NC(GPIO_10), + /* S0iX SLP - goes to EC */ + PAD_GPO(GPIO_10, HIGH), /* EC_IN_RW_OD */ PAD_GPI(GPIO_11, PULL_NONE), /* USI_INT_ODL */ @@ -302,6 +302,8 @@ const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int } static const struct soc_amd_gpio gpio_sleep_table[] = { + /* S0iX SLP */ + PAD_GPO(GPIO_10, LOW), /* PCIE_RST1_L */ PAD_GPO(GPIO_27, LOW), /* diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 818c39bf59..2929c54cdc 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -32,8 +32,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), - /* S0iX SLP - (unused - goes to EC & FPMCU */ - PAD_NC(GPIO_10), + /* S0iX SLP - goes to EC & FPMCU */ + PAD_GPO(GPIO_10, HIGH), /* USI_INT_ODL */ PAD_GPI(GPIO_12, PULL_NONE), /* EN_PWR_TOUCHPAD_PS2 */ @@ -342,6 +342,8 @@ const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int } static const struct soc_amd_gpio gpio_sleep_table[] = { + /* S0iX SLP */ + PAD_GPO(GPIO_10, LOW), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, LOW), /* EN_PWR_CAMERA */ |