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authorTommie <tong.lin@bitland.corp-partner.google.com>2020-03-31 16:24:35 +0800
committerFurquan Shaikh <furquan@google.com>2020-04-07 03:50:08 +0000
commit1b7fc32a54ea962a30da8daee5827003087843ec (patch)
treee5f98dccdad4ccdda3b839f9ce6c2b6d67cfd02c /src/mainboard/google
parent16f6aa81b6aeacc0b9a80a649eeaea96a192ffa2 (diff)
mb/google/octopus/variants/phaser: Disable xHCI compliance mode
Since the first LFPS timeout causes xHCI to enter compliance mode, the SS hub cannot be enumerated. The resolution is to disable xHCI compliance mode. BRANCH=octopus BUG=b:149723583 TEST=Verified USB operation successfully. Signed-off-by: tong.lin <tong.lin@bitland.corp-partner.google.com> Change-Id: I3e6ab6ec0c4865cf2467da900f13d18468ff356f Reviewed-on: https://review.coreboot.org/c/coreboot/+/39968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marco Chen <marcochen@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/octopus/variants/phaser/overridetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb
index 625c2a6a34..b80d0317c8 100644
--- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb
@@ -173,4 +173,7 @@ chip soc/intel/apollolake
end
end # - I2C 7
end
+
+ # Disable xHCI compliance mode
+ register "DisableComplianceMode" = "1"
end