Make MRC vs native a config rather than making a separate chipset for it.

Tested by making lenovo x230 configurable despite pretty MRC bugs.

Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13658
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

6 files changed, 39 insertions, 3 deletions

diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig
index 320981a4de..1fc9c0a3e9 100644
--- a/src/mainboard/google/butterfly/Kconfig
+++ b/src/mainboard/google/butterfly/Kconfig
@@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_RPGA989
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
+	select USE_NATIVE_RAMINIT
 	select SOUTHBRIDGE_INTEL_C216
 	select EC_QUANTA_ENE_KB3940Q
 	select BOARD_ROMSIZE_KB_8192
diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig
index 2d9a9de0de..c9bfa2e562 100644
--- a/src/mainboard/google/link/Kconfig
+++ b/src/mainboard/google/link/Kconfig
@@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_RPGA989
-	select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
+	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select SOUTHBRIDGE_INTEL_C216
 	select BOARD_ROMSIZE_KB_8192
 	select EC_GOOGLE_CHROMEEC
@@ -16,6 +16,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SERIRQ_CONTINUOUS_MODE
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 
+config USE_NATIVE_RAMINIT
+	bool
+	default n
+
 config CHROMEOS
 	select CHROMEOS_VBNV_CMOS
 	select LID_SWITCH
diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig
index e9b55a4ae8..56ebf86fb9 100644
--- a/src/mainboard/google/parrot/Kconfig
+++ b/src/mainboard/google/parrot/Kconfig
@@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_RPGA989
-	select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
+	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select SOUTHBRIDGE_INTEL_C216
 	select EC_COMPAL_ENE932
 	select BOARD_ROMSIZE_KB_8192
diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb
index 0a54566cf6..eacfe57521 100644
--- a/src/mainboard/google/parrot/devicetree.cb
+++ b/src/mainboard/google/parrot/devicetree.cb
@@ -18,6 +18,8 @@ chip northbridge/intel/sandybridge
 	register "gpu_cpu_backlight" = "0x000001d4"
 	register "gpu_pch_backlight" = "0x03aa0000"
 
+	register "max_mem_clock_mhz" = "666"
+
 	device cpu_cluster 0 on
 		chip cpu/intel/socket_rPGA989
 			device lapic 0 on end
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 030f7c467e..5897d13bcf 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -28,6 +28,7 @@
 #include <console/console.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
@@ -158,6 +159,30 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 	*pei_data = pei_data_template;
 }
 
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	/* enabled power  usb oc pin  */
+	{ 0, 0, -1 }, /* P0: Empty */
+	{ 1, 0, 0 }, /* P1: Left USB 1  (OC0) */
+	{ 1, 0, 1 }, /* P2: Left USB 2  (OC1) */
+	{ 1, 0, 1 }, /* P3: Left USB 3  (OC1) */
+	{ 0, 0, -1 }, /* P4: Empty */
+	{ 0, 0, -1 }, /* P5: Empty */
+	{ 0, 0, -1 }, /* P6: Empty */
+	{ 0, 0, -1 }, /* P7: Empty */
+	/* Empty and onboard Ports 8-13, set to un-used pin OC4 */
+	{ 1, 0, -1 }, /* P8: MiniPCIe (WLAN) (no OC) */
+	{ 0, 0, -1 }, /* P9: Empty */
+	{ 1, 0, -1 }, /* P10: Camera (no OC) */
+	{ 0, 0, -1 }, /* P11: Empty */
+	{ 0, 0, -1 }, /* P12: Empty */
+	{ 0, 0, -1 }, /* P13: Empty */
+};
+
+void mainboard_get_spd(spd_raw_data *spd) {
+	read_spd(&spd[0], 0x50);
+	read_spd(&spd[2], 0x52);
+}
+
 void mainboard_config_superio(void)
 {
 }
diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig
index 9dcde5db1f..95c6eaf970 100644
--- a/src/mainboard/google/stout/Kconfig
+++ b/src/mainboard/google/stout/Kconfig
@@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_RPGA989
-	select NORTHBRIDGE_INTEL_IVYBRIDGE_MRC
+	select NORTHBRIDGE_INTEL_IVYBRIDGE
 	select SOUTHBRIDGE_INTEL_C216
 	select EC_QUANTA_IT8518
 	select BOARD_ROMSIZE_KB_8192
@@ -17,6 +17,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select INTEL_INT15
 	select IVYBRIDGE_LVDS
 
+config USE_NATIVE_RAMINIT
+	bool
+	default n
+
 config CHROMEOS
 	select CHROMEOS_VBNV_CMOS