diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-07-12 10:15:22 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-14 12:41:27 +0000 |
| commit | f9a179a66d4d01652b1d21afce8c0473ebf1950b (patch) | |
| tree | e7bdad0033c0782f442cbf664f3977fe87d72699 /src/mainboard/google | |
| parent | 691af099c8f7e593636d8a62265307ddc2976f6f (diff) | |
mb/google/rex: Add chip config for UART devices
This patch ensures LPSS UART 0 is used for the AP serial console as
per Rex Proto 0 schematics dated 07/05.
+-----------+-------------+-------------+
| INTERFACE | PCI (B:D:F) | DEVICE |
+-----------+-------------+-------------+
| UART-0 | 0:0x1e:0 | For AP UART |
+-----------+-------------+-------------+
| UART-1 | 0:0x1e:1 | NA |
+-----------+-------------+-------------+
| UART-2 | 0:0x19:2 | NA |
+-----------+-------------+-------------+
BUG=b:224325352
TEST=Able to get AP UART over LPSS UART0 using emulator.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ice0c81607c758e94d15ea19e346877776a3de7dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/rex/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 7 |
2 files changed, 11 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index ba76553b88..779ebf419c 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -54,6 +54,10 @@ config MEMORY_SOLDERDOWN select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS select HAVE_SPD_IN_CBFS +config UART_FOR_CONSOLE + int + default 0 + config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index c8f113ae9a..f9eb12fe7c 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -1,4 +1,11 @@ chip soc/intel/meteorlake + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + device domain 0 on device ref igpu on end device ref dtt on end |