diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2021-11-12 15:45:27 +0800 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-11-15 10:08:32 +0000 |
| commit | f005c34172413e41e85051a945ca6b0aaccc2c46 (patch) | |
| tree | ba90d37ef9e5492ceb516a453f9a8d28b2d5213f /src/mainboard/google | |
| parent | fb02f0a55e8aa0a1e73d907611f6cf51fa7e76ad (diff) | |
mb/google/brya/var/felwinter: Disable PCIE port 6
PCIE port 6 is empty as per schematics.
BUG=b:206047996
TEST=PCIE port 6 is disabled.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I30fa897c9310c44545e3df670895639a5144e1de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/felwinter/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index dedd192096..5b90b9acb0 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -60,6 +60,7 @@ chip soc/intel/alderlake end end end + device ref pcie_rp6 off end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" |