diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-06-30 15:57:05 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-07 13:48:07 +0000 |
| commit | e88989a5d42cf306b37e3d7c78013475c8338578 (patch) | |
| tree | 3398b26855c175678c98bd23d0878d6752cccea7 /src/mainboard/google | |
| parent | 0e582862c84751c1a517a294091c1eb1ae395543 (diff) | |
mb/google/brya/var/agah: Update FBVDD power-down delay
The EEs have observed the ramp down delay on this signal in more detail
and 40 ms can still meet the sequencing requirements.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I49ef801f7a3fd7945ded63da1399eaf57fd6aef0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/acpi/power.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/agah/variant.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/acpi/power.asl b/src/mainboard/google/brya/acpi/power.asl index e441530165..8232a32e56 100644 --- a/src/mainboard/google/brya/acpi/power.asl +++ b/src/mainboard/google/brya/acpi/power.asl @@ -173,7 +173,7 @@ Method (PGOF, 0, Serialized) /* Ramp down FBVDD (active-low) and let rail discharge to <10% */ \_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN) GPPL (GPIO_FBVDD_PG, 0, 20) - Sleep (150) + Sleep (40) /* Ramp down PEXVDD and let rail discharge to <10% */ \_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN) diff --git a/src/mainboard/google/brya/variants/agah/variant.c b/src/mainboard/google/brya/variants/agah/variant.c index 737cdd241b..b0baab356b 100644 --- a/src/mainboard/google/brya/variants/agah/variant.c +++ b/src/mainboard/google/brya/variants/agah/variant.c @@ -56,7 +56,7 @@ static const struct power_rail_sequence gpu_on_seq[] = { /* In GCOFF entry order (i.e., power-off order) */ static const struct power_rail_sequence gpu_off_seq[] = { - { "FBVDD", FBVDD_PWR_EN, true, FBVDD_PG, 150,}, + { "FBVDD", FBVDD_PWR_EN, true, FBVDD_PG, 40,}, { "PEXVDD", PEXVDD_PWR_EN, false, PEXVDD_PG, 10,}, { "NVVDD+MSVDD", NVVDD_PWR_EN, false, NVVDD_PG, 2,}, { "NV3_3", NV33_PWR_EN, false, NV33_PG, 4,}, |