diff options
| author | Roger Wang <roger2.wang@lcfc.corp-partner.google.com> | 2024-06-14 09:48:44 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-06-18 13:09:19 +0000 |
| commit | e6d2b8a77550d2ab5909e177877ec99dc22555e3 (patch) | |
| tree | c6f4460b8064a0cfebc4db5af56350fffb5740d3 /src/mainboard/google | |
| parent | 1985cac30becf9949cce9c69d9dd4632c920ff2d (diff) | |
mb/google/nissa/var/pujjoga: Update DPTF parameters
Adjust settings as recommended by thermal team.
Update DPTF parameters based on b:346930334
BUG=b:346930334
TEST= built bootleg and verified test result by thermal team
Change-Id: I363eaa72b5190212b014fe4e2c2fca10e2a3f408
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83079
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/pujjoga/overridetree.cb | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb index 951d60ef22..500f21c7fe 100644 --- a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb @@ -156,6 +156,57 @@ chip soc/intel/alderlake }" device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""CPU"" + register "options.tsr[1].desc" = ""DDR"" + register "options.tsr[2].desc" = ""5VCharger"" + + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 60000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 15000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 2000 }, + [2] = { 16, 1500 }, + [3] = { 8, 1000 } + }" + device generic 0 on end + end + end device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" |