diff options
| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2024-04-17 14:37:05 +0800 |
|---|---|---|
| committer | Yu-Ping Wu <yupingso@google.com> | 2024-10-28 03:36:09 +0000 |
| commit | e5519ba7265938701aed8603fd0315d518c64509 (patch) | |
| tree | 22b1de8996cc78ad5f7b6d288bd4f2510be2510e /src/mainboard/google | |
| parent | 97be4e7209bfdaa6c49a21c63f4cb0a18f77bce2 (diff) | |
mb/google/rauru: Add mainboard_needs_pcie_init
Add a trivial mainboard_needs_pcie_init implementation that always
return true. For now, the storage types of rauru SKUs are still unknown.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I6b4f08e15f62da18aa37226075894f2827a9e7ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84697
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/rauru/mainboard.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c index f15dd312f0..a2d725a79f 100644 --- a/src/mainboard/google/rauru/mainboard.c +++ b/src/mainboard/google/rauru/mainboard.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <gpio.h> +#include <soc/pcie.h> #include <soc/usb.h> #include "gpio.h" @@ -13,6 +14,11 @@ static void power_on_fpmcu(void) gpio_output(GPIO_FP_RST_1V8_S3_L, 1); } +bool mainboard_needs_pcie_init(void) +{ + return true; +} + static void mainboard_init(struct device *dev) { setup_usb_host(); |