diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-11-15 20:11:12 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-25 15:03:39 +0000 |
| commit | dd96ab698757c6b6f05612d92f38088e8f7069e5 (patch) | |
| tree | 5baa8f55301af11b68a361a55aa6296675ab4806 /src/mainboard/google | |
| parent | c87814d750073ba89c2a88d8dcc6c7611952ddbc (diff) | |
cpu/intel/haswell: Move chip_ops to cpu cluster
The cpu cluster is always present and it's the proper device to contain
the settings that need to be applied to all cpus. This makes it possible
to remove the fake lapic from devicetrees.
Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/auron/devicetree.cb | 10 | ||||
| -rw-r--r-- | src/mainboard/google/auron/variants/buddy/overridetree.cb | 9 | ||||
| -rw-r--r-- | src/mainboard/google/auron/variants/samus/overridetree.cb | 24 | ||||
| -rw-r--r-- | src/mainboard/google/beltino/devicetree.cb | 9 | ||||
| -rw-r--r-- | src/mainboard/google/jecht/devicetree.cb | 8 | ||||
| -rw-r--r-- | src/mainboard/google/slippy/devicetree.cb | 9 |
6 files changed, 23 insertions, 46 deletions
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 440efdfd69..2ded45256d 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -14,14 +14,10 @@ chip soc/intel/broadwell register "ec_present" = "true" - device cpu_cluster 0 on - ops broadwell_cpu_bus_ops - chip cpu/intel/haswell - register "s0ix_enable" = "1" + chip cpu/intel/haswell + device cpu_cluster 0 on ops broadwell_cpu_bus_ops end - device lapic 0 on end - device lapic 0xacac off end - end + register "s0ix_enable" = "1" end device domain 0 on diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 75bf8ee20f..be96e95d1f 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -11,13 +11,10 @@ chip soc/intel/broadwell register "dq_pins_interleaved" = "true" - device cpu_cluster 0 on - chip cpu/intel/haswell - register "s0ix_enable" = "0" + chip cpu/intel/haswell + device cpu_cluster 0 on end - device lapic 0 on end - device lapic 0xacac off end - end + register "s0ix_enable" = "0" end device domain 0 on diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index cfb48123b4..3de469ecac 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -12,19 +12,17 @@ chip soc/intel/broadwell .backlight_pwm_hz = 200, }" - device cpu_cluster 0 on - chip cpu/intel/haswell - # Disable S0ix for now - register "s0ix_enable" = "0" - - register "vr_config" = "{ - .slow_ramp_rate_set = 3, - .slow_ramp_rate_enable = true, - }" - - device lapic 0 on end - device lapic 0xacac off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on end + + # Disable S0ix for now + register "s0ix_enable" = "0" + + register "vr_config" = "{ + .slow_ramp_rate_set = 3, + .slow_ramp_rate_enable = true, + }" + end device domain 0 on diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 9704cc34d3..18ec581fc0 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -13,13 +13,8 @@ chip northbridge/intel/haswell register "usb_xhci_on_resume" = "true" - device cpu_cluster 0 on - ops haswell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end end device domain 0 on diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index fe09566dbb..59cf071629 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -11,12 +11,8 @@ chip soc/intel/broadwell register "dq_pins_interleaved" = "true" - device cpu_cluster 0 on - ops broadwell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - device lapic 0xacac off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops broadwell_cpu_bus_ops end end device domain 0 on diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index d09d7a16ea..0c1222c4e8 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -15,13 +15,8 @@ chip northbridge/intel/haswell register "usb_xhci_on_resume" = "true" - device cpu_cluster 0 on - ops haswell_cpu_bus_ops - chip cpu/intel/haswell - device lapic 0 on end - # Magic APIC ID to locate this chip - device lapic 0xACAC off end - end + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end end device domain 0 on |