diff options
| author | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2022-03-23 08:48:03 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-03-25 15:58:19 +0000 |
| commit | c4ca20f67ff37b59acfc7779829ac28cd30effb9 (patch) | |
| tree | f1d01febed3439abc237cf9f06316a3ef4aff995 /src/mainboard/google | |
| parent | 66f99f7fa7e7644e2549619b375e758492b601e3 (diff) | |
drivers/i2c/tpm: Work around missing board_cfg in Ti50 FW under 0.15
Ti50 FW under 0.15 is not support board cfg command which causes I2C
errors and entering recovery mode. And ODM stocks are 0.12 pre-flashed.
Add workaround for the old Ti50 chip.
BUG=b:224650720
TEST=no I2C errors in coreboot.
[ERROR] cr50_i2c_read: Address write failed
[INFO ] .I2C stop bit not received
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 199db117bb..259958774a 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -60,6 +60,7 @@ config BOARD_GOOGLE_BASEBOARD_NISSA def_bool n select BOARD_GOOGLE_BRYA_COMMON select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS + select MAINBOARD_NEEDS_I2C_TI50_WORKAROUND select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW |