diff options
| author | Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> | 2023-06-07 13:19:53 +0800 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-06-09 07:18:35 +0000 |
| commit | c3ff7d6900d0ff892360222de486fd6da1930913 (patch) | |
| tree | 0e2361e08baa6bed9cfd33f4257b3dfbadc7e51d /src/mainboard/google | |
| parent | 204a8a4a64f6940c1800407df95b90018df4c1ac (diff) | |
mb/google/nissa/var/uldren: Modify WWAN power sequence
Follow spec[1] to modify WWAN power sequence. The WWAN power sequence
of warm reset is fail. The correct sequence is WWAN_EN should keep high when doing warm reset. Set GPP_D6 to PWROK which is not to do PAD
reset when warm reset.
[1]:
[JDB10] FC ADL-N_WWAN sequence_FM101-GL SDX12 Power Timing
Review_V1.6_20230602.xlsx
BUG=b:285065375
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. power sequence meets spec.
Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75690
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/uldren/gpio.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/uldren/gpio.c b/src/mainboard/google/brya/variants/uldren/gpio.c index c0c438147e..0ea14cd4e4 100644 --- a/src/mainboard/google/brya/variants/uldren/gpio.c +++ b/src/mainboard/google/brya/variants/uldren/gpio.c @@ -20,7 +20,7 @@ static const struct pad_config override_gpio_table[] = { /* C1 : SMBDA==> TCHSCR_RST_L */ PAD_CFG_GPO(GPP_C1, 1, DEEP), /* D6 : SRCCLKREQ1# ==> WWAN_EN */ - PAD_CFG_GPO(GPP_D6, 1, DEEP), + PAD_CFG_GPO(GPP_D6, 1, PWROK), /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), /* D8 : SRCCLKREQ3# ==> NC */ @@ -61,8 +61,6 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B15 : HP_RST_ODL */ PAD_CFG_GPO(GPP_B15, 0, DEEP), - /* D6 : SRCCLKREQ1# ==> WWAN_EN */ - PAD_CFG_GPO(GPP_D6, 1, DEEP), /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), /* F12 : GSXDOUT ==> WWAN_RST_L */ |