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authorSubrata Banik <subratabanik@google.com>2022-02-16 15:45:38 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-02-18 14:53:18 +0000
commitb29d1280238b7c56abbc840b93635e480f5d9727 (patch)
treef63e6ccf3ee7bfd68dd2509e84e0f6f44664f430 /src/mainboard/google
parentdf533e69117a3b6623bb8594e3d2bc35f2391e4d (diff)
mb/google/brya/var/vell: Fix PLD group order
In ec/google/chromeec: Add PLD to EC conn in ACPI table (667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. This patch ensures USB _PLD group numbers are appear in order. BUG=b:216490477 TEST=build coreboot and system boot into OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib0d1be34775c5eacf6cd9b0ec400bd42a93c59e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/brya/variants/vell/overridetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 4daf446f64..b00eb2cbb8 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -381,7 +381,7 @@ chip soc/intel/alderlake
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C3 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- register "group" = "ACPI_PLD_GROUP(5, 1)"
+ register "group" = "ACPI_PLD_GROUP(4, 1)"
device ref tcss_usb3_port4 on end
end
end
@@ -416,7 +416,7 @@ chip soc/intel/alderlake
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C3 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- register "group" = "ACPI_PLD_GROUP(5, 1)"
+ register "group" = "ACPI_PLD_GROUP(4, 1)"
device ref usb2_port5 on end
end
chip drivers/usb/acpi