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authorFrank Wu <frank_wu@compal.corp-partner.google.com>2021-08-03 17:30:27 +0800
committerKarthik Ramasubramanian <kramasub@google.com>2021-08-16 14:59:01 +0000
commitae02727c322e162fc690ce5c13fe39cac5c30856 (patch)
tree398a64a4d7a53a07237f46001035428d5a7e76b9 /src/mainboard/google
parentc822b9519ec1a8a378af39e713754c8ff8a1ff83 (diff)
mb/google/dedede: Create driblee variant
Create the driblee variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:191732473 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DRIBLEE Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I1ad9a4e0cf7999337b55d62d5cc94e4f6c2e98f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/dedede/Kconfig2
-rw-r--r--src/mainboard/google/dedede/Kconfig.name5
-rw-r--r--src/mainboard/google/dedede/variants/driblee/include/variant/ec.h8
-rw-r--r--src/mainboard/google/dedede/variants/driblee/include/variant/gpio.h8
-rw-r--r--src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc5
-rw-r--r--src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt1
-rw-r--r--src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt11
-rw-r--r--src/mainboard/google/dedede/variants/driblee/overridetree.cb43
8 files changed, 83 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index c2c0f5c8d3..5c0b0df3b6 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -114,6 +114,7 @@ config MAINBOARD_PART_NUMBER
default "Cappy2" if BOARD_GOOGLE_CAPPY2
default "Bugzzy" if BOARD_GOOGLE_BUGZZY
default "Corori" if BOARD_GOOGLE_CORORI
+ default "Driblee" if BOARD_GOOGLE_DRIBLEE
config MAX_CPUS
int
@@ -153,6 +154,7 @@ config VARIANT_DIR
default "cappy2" if BOARD_GOOGLE_CAPPY2
default "bugzzy" if BOARD_GOOGLE_BUGZZY
default "corori" if BOARD_GOOGLE_CORORI
+ default "driblee" if BOARD_GOOGLE_DRIBLEE
endif #BOARD_GOOGLE_BASEBOARD_DEDEDE
diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name
index 98a656bdd3..4dc0d0dd8e 100644
--- a/src/mainboard/google/dedede/Kconfig.name
+++ b/src/mainboard/google/dedede/Kconfig.name
@@ -171,3 +171,8 @@ config BOARD_GOOGLE_CORORI
bool "-> Corori"
select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
select BASEBOARD_DEDEDE_LAPTOP
+
+config BOARD_GOOGLE_DRIBLEE
+ bool "-> Driblee"
+ select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
+ select BASEBOARD_DEDEDE_LAPTOP
diff --git a/src/mainboard/google/dedede/variants/driblee/include/variant/ec.h b/src/mainboard/google/dedede/variants/driblee/include/variant/ec.h
new file mode 100644
index 0000000000..08870e0627
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/driblee/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/dedede/variants/driblee/include/variant/gpio.h b/src/mainboard/google/dedede/variants/driblee/include/variant/gpio.h
new file mode 100644
index 0000000000..9078664608
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/driblee/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc b/src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc
new file mode 100644
index 0000000000..b0ca2223a8
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+## This is an auto-generated file. Do not edit!!
+## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder.spd.hex
diff --git a/src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..fa247902ee
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name ID to assign
diff --git a/src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt
new file mode 100644
index 0000000000..e4258b530d
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# gen_part_id tool from util/spd_tools/{ddr4,lp4x}.
+# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions.
+
+# Part Name
diff --git a/src/mainboard/google/dedede/variants/driblee/overridetree.cb b/src/mainboard/google/dedede/variants/driblee/overridetree.cb
new file mode 100644
index 0000000000..cbad0d29a0
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/driblee/overridetree.cb
@@ -0,0 +1,43 @@
+chip soc/intel/jasperlake
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| I2C0 | Trackpad |
+ #| I2C1 | Digitizer |
+ #| I2C2 | Touchscreen |
+ #| I2C3 | Camera |
+ #| I2C4 | Audio |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[4] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ }"
+
+ register "SerialIoGSpiMode[PchSerialIoIndexGSPI0]" = "PchSerialIoDisabled" # Disable GSPI0
+ register "SerialIoGSpiCsMode[PchSerialIoIndexGSPI0]" = "0"
+
+ device domain 0 on
+ device pci 15.0 on end
+ device pci 1e.2 off end # GSPI 0
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end # Discrete TPM
+ end # chip drivers/pc80/tpm
+ end # PCH eSPI
+ end
+end