diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2022-10-16 13:55:33 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-18 13:12:00 +0000 |
| commit | ad60b7fb563f644b425f3b22d8d3bf443bc1e905 (patch) | |
| tree | e5b9bd8ef5a0eecc5597977d9ae56c8ad6b21f6b /src/mainboard/google | |
| parent | 856a3f4a3c01fb2de022cec3e4c8e95eeeeb4345 (diff) | |
mb/google/reef: Fix WiFi SAR options
SAR-related Kconfigs are only used by ChromeOS, and should be guarded
properly as such (as most other boards do).
TEST=build reef w/o CONFIG_CHROMEOS, verify SAR-related Kconfigs not
selected.
Change-Id: I4fe3092e620bcbc33b0411ea69e55154fc118aa4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68457
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/reef/Kconfig | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 47d111431d..fb02631650 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -5,7 +5,6 @@ config BOARD_GOOGLE_BASEBOARD_REEF select DRIVERS_I2C_DA7219 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID - select DSAR_ENABLE select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC @@ -17,11 +16,9 @@ config BOARD_GOOGLE_BASEBOARD_REEF select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 - select SAR_ENABLE select SOC_INTEL_APOLLOLAKE select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 - select USE_SAR config BOARD_GOOGLE_REEF select BOARD_GOOGLE_BASEBOARD_REEF @@ -40,6 +37,14 @@ config BOARD_GOOGLE_CORAL if BOARD_GOOGLE_BASEBOARD_REEF +config CHROMEOS_WIFI_SAR + bool "Enable SAR options for ChromeOS build" + depends on CHROMEOS + default y if CHROMEOS + select DSAR_ENABLE + select SAR_ENABLE + select USE_SAR + config DRIVER_TPM_I2C_BUS hex default 0x2 |