mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`

The dt option `speed_shift_enable` is obsolete now. Drop it.

Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>

17 files changed, 0 insertions, 28 deletions

diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index b7aa11da31..4713589608 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -136,9 +136,6 @@ chip soc/intel/jasperlake
 	register "DdiPortBDdc" = "1"
 	register "DdiPortCDdc" = "1"
 
-	# Enable Speed Shift Technology support
-	register "speed_shift_enable" = "1"
-
 	# Enable DPTF
 	register "dptf_enable" = "1"
 
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
index 775c54815e..bbb63bcc61 100644
--- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
@@ -134,9 +134,6 @@ chip soc/intel/tigerlake
 	register "gpio_pm[3]" = "0"
 	register "gpio_pm[4]" = "0"
 
-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Graphics
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index aa6af87c3a..de3b5ca8ea 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -40,7 +40,6 @@ chip soc/intel/cannonlake
 	# USB2 PHY Power gating
 	register "PchUsb2PhySusPgDisable" = "1"
 
-	register "speed_shift_enable" = "1"
 	register "s0ix_enable" = "1"
 	register "dptf_enable" = "1"
 	register "power_limits_config" = "{
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index a2550bb475..519e53ba6c 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -227,7 +227,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 	}"
 
-	register "speed_shift_enable" = "1"
 	register "dptf_enable" = "1"
 	register "power_limits_config" = "{
 		.tdp_pl1_override = 7,
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 9c11e807e8..703ef5b775 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -305,7 +305,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 	}"
 
-	register "speed_shift_enable" = "1"
 	register "power_limits_config" = "{
 		.tdp_psyspl2 = 90,
 		.psys_pmax = 120,
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 12312e980a..2dfb71f2c0 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -30,9 +30,6 @@ chip soc/intel/skylake
 	register "gen1_dec" = "0x00fc0801"
 	register "gen2_dec" = "0x000c0201"
 
-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# Enable DPTF
 	register "dptf_enable" = "1"
 
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 10ad029e40..cdd83df114 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -29,8 +29,6 @@ chip soc/intel/cannonlake
 	register "satapwroptimize" = "1"
 	# Enable System Agent dynamic frequency
 	register "SaGv" = "SaGv_Enabled"
-	# Enable Speed Shift Technology support
-	register "speed_shift_enable" = "1"
 	# Enable S0ix
 	register "s0ix_enable" = "1"
 	# Enable DPTF
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 9f9d9518d6..3797fb0135 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -59,7 +59,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
 	register "PmTimerDisabled" = "1"
 
-	register "speed_shift_enable" = "1"
 	register "power_limits_config" = "{
 		.tdp_pl1_override = 7,
 		.tdp_pl2_override = 15,
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 0dc9131aaf..0b3d6c0346 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -246,7 +246,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 	}"
 
-	register "speed_shift_enable" = "1"
 	# PL2 override 15W for KBL-Y
 	register "power_limits_config" = "{
 		.tdp_pl2_override = 15,
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 167bd036d6..d408f9ee93 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -266,8 +266,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 	}"
 
-	register "speed_shift_enable" = "1"
-
 	register "tcc_offset" = "3"     # TCC of 97C
 	register "power_limits_config" = "{
 		.psys_pmax = 101,
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index ed21492946..b7d171b6ff 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -268,7 +268,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 	}"
 
-	register "speed_shift_enable" = "1"
 	# PL2 override 15W for KBL-Y
 	register "power_limits_config" = "{
 		.tdp_pl2_override = 15,
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 0a29601c39..ab1588af80 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -54,8 +54,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
 	register "PmTimerDisabled" = "1"
 
-	# Set speed_shift_enable to 1 to enable P-States, and 0 to disable
-	register "speed_shift_enable" = "1"
 	register "power_limits_config" = "{
 		.tdp_pl1_override = 7,
 		.tdp_pl2_override = 18,
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 591e0fb478..2334a179df 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -225,7 +225,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 	}"
 
-	register "speed_shift_enable" = "1"
 	# PL2 override 18W for AML-Y
 	register "power_limits_config" = "{
 		.tdp_pl2_override = 18,
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index b3570d73b2..c69875597d 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -247,7 +247,6 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
 	}"
 
-	register "speed_shift_enable" = "1"
 	# PL2 override 15W for KBL-Y
 	register "power_limits_config" = "{
 		.tdp_pl2_override = 15,
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index b1d9a36159..3ff9b30637 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -29,7 +29,6 @@ chip soc/intel/cannonlake
 	# USB2 PHY Power gating
 	register "PchUsb2PhySusPgDisable" = "1"
 
-	register "speed_shift_enable" = "1"
 	register "s0ix_enable" = "1"
 	register "dptf_enable" = "1"
 	register "satapwroptimize" = "1"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index e1ee6c9be8..17d0127ce6 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -32,7 +32,6 @@ chip soc/intel/cannonlake
 	# USB2 PHY Power gating
 	register "PchUsb2PhySusPgDisable" = "1"
 
-	register "speed_shift_enable" = "1"
 	register "s0ix_enable" = "1"
 	register "dptf_enable" = "1"
 	register "satapwroptimize" = "1"
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index b76f627873..2a62505757 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -230,9 +230,6 @@ chip soc/intel/tigerlake
 	register "DdiPort3Ddc" = "0"
 	register "DdiPort4Ddc" = "0"
 
-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# Enable S0ix
 	register "s0ix_enable" = "1"