diff options
| author | Ryan Lin <ryan.lin@intel.com> | 2021-10-05 11:38:22 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-10-07 14:53:47 +0000 |
| commit | a45377e83e720886616ed50ebf32bdcbb9d945cb (patch) | |
| tree | ddc5a0e29a9dccbf5ff6312ca6a6ab1d9d9ce074 /src/mainboard/google | |
| parent | e5824ff2a90199b32941fe136d080f3f753c3b7f (diff) | |
mb/google/brya: Add PsysPmax setting to 145W
This patch adds the setting of PsysPmax to 145W according to
the brya board design.
BUG=b:195615830
TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS
Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd
Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/brya0/overridetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 41d1018727..ad2399bb11 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -32,6 +32,8 @@ end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" + register "PsysPmax" = "145" + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port |