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authorRob Barnes <robbarnes@google.com>2021-12-13 08:35:28 -0700
committerFelix Held <felix-coreboot@felixheld.de>2021-12-15 17:07:14 +0000
commita1430c340ead7cc812a64a8269b712791ae598d9 (patch)
tree0d70e15aab7f595d5bc8c7f7a51074d5fb6b22fa /src/mainboard/google
parent540951e3740cae8796e551763356eb2d23f82c6a (diff)
mb/google/guybrush: Set TPM to to be kernel power managed.
Set TPM power_managed_mode to TPM_KERNEL_POWER_MANAGED. This will cause the TPM kernel driver to send a shutdown command before s0i3 entry. This change depends on S0i3 verstage running and reinitializing the TPM. BUG=b:200578885 BRANCH=None TEST=TPM shutdown sent during s0i3 entry on guybrush Change-Id: I206022cc2a29690186206966c5d45bd55c303248 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index 7fb3c7e6c8..ac2856e93b 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -342,6 +342,8 @@ chip soc/amd/cezanne
register "hid" = ""GOOG0005""
register "desc" = ""Cr50 TPM""
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_85)"
+ register "power_managed_mode" = "CONFIG(PSP_S0I3_RESUME_VERSTAGE) ?
+ TPM_KERNEL_POWER_MANAGED : TPM_DEFAULT_POWER_MANAGED"
device i2c 50 alias cr50 on end
end
end