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authorRob Barnes <robbarnes@google.com>2021-09-02 08:52:42 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-09-05 19:21:15 +0000
commit888f3030376195a702e4335a08763828fb65d0b2 (patch)
tree5a93448cccb92cff308b82d0f77c376040c6184e /src/mainboard/google
parent26a77eb4d1074327282eeb65407aec130c0bb3ba (diff)
mb/google/guybrush: Set eSPI alert as dedicated open drain
Guybrush based boards must usa a dedicated eSPI alert#. Must be open drain to prevent power leaks. Keep guybrush reference board in-band since alert# may not be connected. BUG=b:198409370 TEST=Build guybrush and nipperkin, boot guybrush BRANCH=None Change-Id: I4b23bfc6a1167aebfde5acd524fda043b63163dc Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/devicetree.cb2
-rw-r--r--src/mainboard/google/guybrush/variants/guybrush/overridetree.cb3
2 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index df8bd2afd3..a0d51144b8 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -36,7 +36,7 @@ chip soc/amd/cezanne
.io_mode = ESPI_IO_MODE_QUAD,
.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
.crc_check_enable = 1,
- .alert_pin = ESPI_ALERT_PIN_IN_BAND,
+ .alert_pin = ESPI_ALERT_PIN_OPEN_DRAIN,
.periph_ch_en = 1,
.vw_ch_en = 1,
.oob_ch_en = 0,
diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
index 88c7d42059..e7329171e0 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
@@ -168,4 +168,7 @@ chip soc/amd/cezanne
end
end
+ # TODO(b/198596430): Disable in-band alerts after majority boards are reworked
+ register "common_config.espi_config.alert_pin" = "ESPI_ALERT_PIN_IN_BAND"
+
end # chip soc/amd/cezanne