diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-02-23 13:11:36 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-02-25 17:16:21 +0000 |
| commit | 74dfbd09feea216da5a91f6768038de8cf37d8aa (patch) | |
| tree | ba9674f882df3d336c00f13edca872724edd7622 /src/mainboard/google | |
| parent | 59881a62c1100c6028919cca949e9736b9e44d6d (diff) | |
mb/google/volteer: Fix eldrid DPTF's passive and critical policies
Because the entries were formatted differently to the baseboard, the
devicetree overrides didn't work as intended, and all 5 entries from
the baseboard were included, and then the overrides were applied, but
the baseboard's entries were kept, so there were duplicate ACPI
entries, which causes errors when parsing the table.
Fixes: 5f30ae3714d ("mb/google/volteer: update thermal table for Eldrid")
BUG=b:181034399
TEST=compile, verify static.c is correct now
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I32fe2eae591ed4d3c08378977c463327f7ee1100
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51044
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/volteer/variants/eldrid/overridetree.cb | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 6760361355..ed15755953 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -100,12 +100,14 @@ chip soc/intel/tigerlake register "policies.active" = "{[0] = {.target=DPTF_NONE}}" ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU,CPU,87,5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60.8,6000)" + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU,CPU,87,5000), + [1] = DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60.8,6000)}" ## Critical Policy - register "policies.critical[0]" = "DPTF_CRITICAL(CPU,100,SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_2,75,SHUTDOWN)" + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU,100,SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_2,75,SHUTDOWN)}" ## Power Limits Control # 3-15W PL1 in 200mW increments, avg over 26-34s interval |