diff options
| author | Hannah Williams <hannah.williams@intel.com> | 2015-07-27 19:46:34 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-28 20:44:34 +0100 |
| commit | 73600e31992bf115b47de37dcd597b8560b05751 (patch) | |
| tree | df62379441da7a88e801126142659236c610bb35 /src/mainboard/google | |
| parent | 2b9696239fb3ee6551ae51aa85080206cce9bfed (diff) | |
soc/braswell: Fix for auto wake from S5
Disabling S5 wake from touch panel and trackpad
TEST=Build and boot the platform.
TEST=Poweroff platform -> enter PG3 -> remove AC -> close Lid
Plug AC in -> EC boots up and AP will shutdown the platform
and open Lid -> platform boots to OS.
Change-Id: I7b661a9f1327b97d904bac40e78612648f353e39
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/288970
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-on: https://review.coreboot.org/13425
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/cyan/smihandler.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 04cc8993a8..9b363cacc1 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -28,6 +28,8 @@ /* The wake gpio is SUS_GPIO[0]. */ #define WAKE_GPIO_EN SUS_GPIO_EN0 +#define GPIO_SUS7_WAKE_MASK (1 << 12) +#define GPIO_SUS1_WAKE_MASK (1 << 13) int mainboard_io_trap_handler(int smif) { @@ -96,6 +98,9 @@ void mainboard_smi_gpi(uint32_t alt_gpio_smi) void mainboard_smi_sleep(uint8_t slp_typ) { + void *addr; + uint32_t mask; + /* Disable USB charging if required */ switch (slp_typ) { case 3: @@ -125,6 +130,16 @@ void mainboard_smi_sleep(uint8_t slp_typ) /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); #endif + + /* Disabling wake from SUS_GPIO1 (TOUCH INT) and + * SUS_GPIO7 (TRACKPAD INT) in North bank as they are not + * valid S5 wake sources + */ + addr = (void *)(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPNORTH + + GPIO_WAKE_MASK_REG0); + mask = ~(GPIO_SUS1_WAKE_MASK | GPIO_SUS7_WAKE_MASK); + write32(addr, read32(addr) & mask); + break; } |