coreboot rush: Add dram init code

Add support for initializing dram within romstage. This is an essential before we
move to the armv8 core.

BUG=None
BRANCH=None
TEST=Compiles succesfully for rush. Tried writing to and reading value from the
base of sdram and it worked fine. Also tested with primitive_memtest CL:
https://chromium-review.googlesource.com/#/c/186309/5

Original-Change-Id: I67ec04c766e249c9727b0cf2ba216522c862c2f5
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205823
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 33c468b16e7ccd8cf9266d6a9ca30c02da104821)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I4baface2c109ca74f85f43a25508677c46c64159
Reviewed-on: http://review.coreboot.org/8574
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

4 files changed, 93 insertions, 0 deletions

diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc
index 4c6273f99f..746af11392 100644
--- a/src/mainboard/google/rush/Makefile.inc
+++ b/src/mainboard/google/rush/Makefile.inc
@@ -34,5 +34,6 @@ bootblock-y += reset.c
 
 romstage-y += romstage.c
 romstage-y += reset.c
+romstage-y += sdram_configs.c
 
 ramstage-y += mainboard.c
\ No newline at end of file
diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c
index f0de9c0dfb..9db52989f7 100644
--- a/src/mainboard/google/rush/romstage.c
+++ b/src/mainboard/google/rush/romstage.c
@@ -22,6 +22,9 @@
 #include <console/console.h>
 #include <arch/exception.h>
 
+#include "sdram_configs.h"
+#include <soc/nvidia/tegra132/sdram.h>
+
 void main(void)
 {
 	void *entry;
@@ -31,6 +34,10 @@ void main(void)
 
 	printk(BIOS_INFO, "T132: romstage here\n");
 
+	sdram_init(get_sdram_config());
+
+	printk(BIOS_INFO, "T132 romstage: sdram_init done\n");
+
 	while (1);
 
         entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
diff --git a/src/mainboard/google/rush/sdram_configs.c b/src/mainboard/google/rush/sdram_configs.c
new file mode 100644
index 0000000000..18386ac53e
--- /dev/null
+++ b/src/mainboard/google/rush/sdram_configs.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <soc/nvidia/tegra132/sdram.h>
+#include "sdram_configs.h"
+
+static struct sdram_params sdram_configs[] = {
+#include "bct/sdram-hynix-2GB-924.inc"			/* ram_code = 0000 */
+#include "bct/sdram-hynix-4GB-792.inc"			/* ram_code = 0001 */
+#include "bct/sdram-unused.inc"				/* ram_code = 0010 */
+#include "bct/sdram-unused.inc"				/* ram_code = 0011 */
+#include "bct/sdram-unused.inc"				/* ram_code = 0100 */
+#include "bct/sdram-unused.inc"				/* ram_code = 0101 */
+#include "bct/sdram-unused.inc"				/* ram_code = 0110 */
+#include "bct/sdram-unused.inc"				/* ram_code = 0111 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1000 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1001 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1010 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1011 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1100 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1101 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1110 */
+#include "bct/sdram-unused.inc"				/* ram_code = 1111 */
+};
+
+const struct sdram_params *get_sdram_config()
+{
+	uint32_t ramcode = sdram_get_ram_code();
+	/*
+	 * If we need to apply some special hacks to RAMCODE mapping (ex, by
+	 * board_id), do that now.
+	 */
+
+	printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode);
+	if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) ||
+	    sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused)
+		die("Invalid RAMCODE.");
+
+	return &sdram_configs[ramcode];
+}
diff --git a/src/mainboard/google/rush/sdram_configs.h b/src/mainboard/google/rush/sdram_configs.h
new file mode 100644
index 0000000000..e00e9ca04c
--- /dev/null
+++ b/src/mainboard/google/rush/sdram_configs.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __MAINBOARD_GOOGLE_RUSH_SDRAM_CONFIG_H__
+#define __MAINBOARD_GOOGLE_RUSH_SDRAM_CONFIG_H__
+
+#include <soc/nvidia/tegra132/sdram_param.h>
+
+/* Loads SDRAM configurations for current system. */
+const struct sdram_params *get_sdram_config(void);
+
+#endif  /* __MAINBOARD_GOOGLE_RUSH_SDRAM_CONFIG_H__ */