diff options
| author | Weimin Wu <wuweimin@huaqin.corp-partner.google.com> | 2023-12-08 10:58:20 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-14 13:07:13 +0000 |
| commit | 6215ef47cdc05445fae6070cea27dba9dca40a24 (patch) | |
| tree | 69920ff2f3cc7d30b45a03973b3121821c69183b /src/mainboard/google | |
| parent | 133e3ee6610e1a2bac19557119f00a736d12baeb (diff) | |
mb/google/nissa/var/anraggar: Enable USB3 Port3 for WWAN (LTE)
1. Ref to SCH, LTE use USB3 Port3, enable it.
2. Explicitly define the use of USB3 Port1 & USB3 Port2.
BUG=b:315061146
TEST=can pass PCIe Hardware Compliance Test
Change-Id: I03d6925020012fa740bbd0168a2f5b02ea6763b4
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/anraggar/overridetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index bc31532732..9ceed5446d 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -416,6 +416,10 @@ chip soc/intel/alderlake register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch) register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch) register "usb2_ports[9]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB)) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE) chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi |