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authorTao Xia <xiatao5@huaqin.corp-partner.google.com>2021-07-05 14:23:01 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-07-07 14:58:17 +0000
commit5aa511931f5a1069be1803f4f8fb4182e8d779ab (patch)
treefa0fc5cc8bda5d7afa8642b416321d2093d558a3 /src/mainboard/google
parent6c1bdc8939e5210d5ef0d4b07896e77ce9548983 (diff)
mb/google/dedede/var/storo: Update DPTF parameters
Update DPTF parameters from internal thermal team. BUG=b:180875582 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I6d87bc63a66ff38bc2f706d58b8537c052bf4594 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/dedede/variants/storo/overridetree.cb8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index 7ddadbded8..e8246522b9 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -77,16 +77,16 @@ chip soc/intel/jasperlake
.tdp_pl2_override = 20,
}"
- register "tcc_offset" = "5" # TCC of 100C
+ register "tcc_offset" = "10" # TCC of 95C
device domain 0 on
device pci 04.0 on
chip drivers/intel/dptf
## Passive Policy
register "policies.passive" = "{
- [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 3000),
- [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 60, 3000),
- [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 60, 3000),}"
+ [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 67, 3000),
+ [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 67, 3000),
+ [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 67, 3000),}"
## Critical Policy
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),