diff options
| author | Raihow Shi <raihow_shi@wistron.corp-partner.google.com> | 2022-04-12 10:58:41 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-19 13:08:53 +0000 |
| commit | 5215f2ffcb04d2c5782f46807d41e2ffb361ed2b (patch) | |
| tree | 5e97a0bf1e6541b2e0ff70250edcf10ad9e585ef /src/mainboard/google | |
| parent | 40c47b24a450b63af9cbba1a2ffbf04cd282076c (diff) | |
mb/google/brask/variants/moli: update type-c setting in overridetree
Add conn1 for pch_espi and add type-c port2 for pmc_mux.
BUG=b:220814038
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Idfd7b761496a110f34838abb0fd408b37d390ba2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/moli/overridetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index e9bc846ce8..eb13b06174 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -113,6 +113,7 @@ chip soc/intel/alderlake device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] + use conn1 as mux_conn[1] device pnp 0c09.0 on end end end @@ -124,6 +125,11 @@ chip soc/intel/alderlake use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end end end end |