diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2014-06-10 10:05:03 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-01-04 00:05:44 +0100 |
| commit | 5106b9dbb7b5cf0f61e763706c868054a1408e31 (patch) | |
| tree | 14277618199d8ff73e3be1cbaea14951d0432736 /src/mainboard/google | |
| parent | ef57a22163519431dc0951f2ccc857f1027d7109 (diff) | |
samus: Minor fixes for P1.9 boards
- Put SSD into reset on transition to S3/S5 to prevent leakage
- Fix GPIO number for wlan disable used in smihandler
- Enable generic hub driver in libpayload
- Fix comment in devicetree about S0ix
BUG=chrome-os-partner:28502
BRANCH=None
TEST=Build and boot on samus
Original-Change-Id: Idce566d0f22622d36697be54ab51cacb576c5d6d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203185
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c0dd822babee3d766eff1735687d14e63380f702)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Idc2da99fce817aaf893f031ffbb4ac4a2ade31b0
Reviewed-on: http://review.coreboot.org/8048
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/samus/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/samus/smihandler.c | 8 |
2 files changed, 7 insertions, 3 deletions
diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb index ce13a1daf2..95ab44be1e 100644 --- a/src/mainboard/google/samus/devicetree.cb +++ b/src/mainboard/google/samus/devicetree.cb @@ -52,7 +52,7 @@ chip soc/intel/broadwell # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP register "icc_clock_disable" = "0x013b0000" - # Enable S0ix + # Disable S0ix for now register "s0ix_enable" = "0" device cpu_cluster 0 on diff --git a/src/mainboard/google/samus/smihandler.c b/src/mainboard/google/samus/smihandler.c index b43b46a427..932d606ba0 100644 --- a/src/mainboard/google/samus/smihandler.c +++ b/src/mainboard/google/samus/smihandler.c @@ -32,8 +32,8 @@ #include <broadwell/smm.h> #include "ec.h" -/* GPIO46 controls the WLAN_DISABLE_L signal. */ -#define GPIO_WLAN_DISABLE_L 46 +#define GPIO_SSD_RESET_L 47 +#define GPIO_WLAN_DISABLE_L 42 #define GPIO_LTE_DISABLE_L 59 int mainboard_io_trap_handler(int smif) @@ -103,6 +103,8 @@ void mainboard_smi_sleep(u8 slp_typ) 1, USB_CHARGE_MODE_DISABLED); } + /* Put SSD in reset to prevent leak. */ + set_gpio(GPIO_SSD_RESET_L, 0); /* Prevent leak from standby rail to WLAN rail in S3. */ set_gpio(GPIO_WLAN_DISABLE_L, 0); /* Disable LTE */ @@ -119,6 +121,8 @@ void mainboard_smi_sleep(u8 slp_typ) 1, USB_CHARGE_MODE_DISABLED); } + /* Put SSD in reset to prevent leak. */ + set_gpio(GPIO_SSD_RESET_L, 0); /* Prevent leak from standby rail to WLAN rail in S5. */ set_gpio(GPIO_WLAN_DISABLE_L, 0); /* Disable LTE */ |