diff options
| author | Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> | 2023-05-22 18:52:38 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-24 18:28:03 +0000 |
| commit | 3b82131c2822be01feae46e77d51f32b286f04fe (patch) | |
| tree | c448e2dd357a5d750d2cf5fb8af87cebf095f465 /src/mainboard/google | |
| parent | 3afa59310308ed1f57ef68c725e01e62fe8ad1ea (diff) | |
mb/google/Screebo: Enable AUX DC biasing on C0
SKU1A C0 has no redriver, so enable SBU muxing in the SoC.
BUG=b:283044004
BRANCH=none
TEST=Voltages are correct on the C0 and C1 AUX bias pins
Change-Id: I18b4ade2c60c270855fb2e733a9201539e08d8ba
Signed-off-by: mike <mike5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/rex/variants/screebo/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/screebo/overridetree.cb | 8 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/screebo/variant.c | 22 |
3 files changed, 31 insertions, 0 deletions
diff --git a/src/mainboard/google/rex/variants/screebo/Makefile.inc b/src/mainboard/google/rex/variants/screebo/Makefile.inc index 228886c1bb..192041b425 100644 --- a/src/mainboard/google/rex/variants/screebo/Makefile.inc +++ b/src/mainboard/google/rex/variants/screebo/Makefile.inc @@ -3,3 +3,4 @@ bootblock-y += gpio.c romstage-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index ee59f6a342..691aafd9e9 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -1,3 +1,11 @@ +fw_config + field MB_CONFIG 5 7 + option MB_UNKNOWN 0 + option MB_TYPEC 1 + option MB_TBT 2 + end +end + chip soc/intel/meteorlake register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 diff --git a/src/mainboard/google/rex/variants/screebo/variant.c b/src/mainboard/google/rex/variants/screebo/variant.c new file mode 100644 index 0000000000..4044fd4025 --- /dev/null +++ b/src/mainboard/google/rex/variants/screebo/variant.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <fw_config.h> +#include <baseboard/variants.h> + +void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +{ + /* SOC Aux orientation override: + * This is a bitfield that corresponds to up to 4 TCSS ports. + * Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + * TcssAuxOri = 0101b + * Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + * Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + * motherboard to USBC connector + */ + if (fw_config_probe(FW_CONFIG(MB_CONFIG, MB_TYPEC))) { + config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_C16; + config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_C17; + config->tcss_aux_ori = 0x04; + } +} |