mb/google/rex: Enable building for Chrome OS

Enable building for Chrome OS and add associated ACPI configuration.

BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I75cb2d30d699166a056ed9d3c0779816b733b0d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64621
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 61 insertions, 0 deletions

diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index dbccce6770..3ce79cb1e7 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -9,6 +9,7 @@ config BOARD_GOOGLE_BASEBOARD_REX
 	select BOARD_GOOGLE_REX_COMMON
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_ESPI
+	select MAINBOARD_HAS_CHROMEOS
 	select SOC_INTEL_METEORLAKE
 	select SYSTEM_TYPE_LAPTOP
 
@@ -22,6 +23,7 @@ config BASEBOARD_DIR
 	default "rex" if BOARD_GOOGLE_BASEBOARD_REX
 
 config CHROMEOS
+	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
 	select VBOOT_LID_SWITCH
 
diff --git a/src/mainboard/google/rex/Makefile.inc b/src/mainboard/google/rex/Makefile.inc
index cab45dfa2a..051169535e 100644
--- a/src/mainboard/google/rex/Makefile.inc
+++ b/src/mainboard/google/rex/Makefile.inc
@@ -1,8 +1,12 @@
 bootblock-y += bootblock.c
 
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
 romstage-y += romstage.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 ramstage-y += mainboard.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ec.c
 
 VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
diff --git a/src/mainboard/google/rex/chromeos.c b/src/mainboard/google/rex/chromeos.c
new file mode 100644
index 0000000000..5c99371eb1
--- /dev/null
+++ b/src/mainboard/google/rex/chromeos.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <bootmode.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <types.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+		{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+	return gpio_get(GPIO_PCH_WP);
+}
+
+int get_ec_is_trusted(void)
+{
+	/* EC is trusted if not in RW. */
+	return !gpio_get(GPIO_EC_IN_RW);
+}
diff --git a/src/mainboard/google/rex/mainboard.c b/src/mainboard/google/rex/mainboard.c
index f3fef836dc..552c0d3dc8 100644
--- a/src/mainboard/google/rex/mainboard.c
+++ b/src/mainboard/google/rex/mainboard.c
@@ -1,8 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <acpi/acpi.h>
 #include <baseboard/variants.h>
 #include <device/device.h>
 #include <ec/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 static void mainboard_init(void *chip_info)
 {
@@ -11,6 +13,17 @@ static void mainboard_init(void *chip_info)
 	pads = variant_gpio_table(&num);
 	gpio_configure_pads(pads, num);
 }
+
+static void mainboard_fill_ssdt(const struct device *dev)
+{
+	/* TODO: Add mainboard-specific SSDT entries */
+}
+
+static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t)
+{
+	/* TODO: Add mainboard-smbios entries */
+}
+
 static void mainboard_dev_init(struct device *dev)
 {
 	mainboard_ec_init();
@@ -19,6 +32,8 @@ static void mainboard_dev_init(struct device *dev)
 static void mainboard_enable(struct device *dev)
 {
 	dev->ops->init = mainboard_dev_init;
+	dev->ops->get_smbios_strings = mainboard_smbios_strings;
+	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h
index a2fc805287..c2dbe5401d 100644
--- a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h
@@ -5,6 +5,7 @@
 
 #include <soc/gpio.h>
 #include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* The next set of functions return the gpio table and fill in the number of entries for
  * each table.
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/gpio.c b/src/mainboard/google/rex/variants/baseboard/rex/gpio.c
index d9c31666ae..8efb7abc7b 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/gpio.c
+++ b/src/mainboard/google/rex/variants/baseboard/rex/gpio.c
@@ -32,3 +32,8 @@ const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
 	*num = 0;
 	return NULL;
 }
+
+static const struct cros_gpio cros_gpios[] = {
+};
+
+DECLARE_WEAK_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h b/src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h
index 0011ebb6ed..ce389fe7d7 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h
+++ b/src/mainboard/google/rex/variants/baseboard/rex/include/baseboard/gpio.h
@@ -6,6 +6,11 @@
 #include <soc/gpe.h>
 #include <soc/gpio.h>
 
+/* Fixme: Update proper GPIO number based on schematics */
+/* WP signal to PCH */
+#define GPIO_PCH_WP	0
+/* EC in RW or RO */
+#define GPIO_EC_IN_RW	0
 /* GPIO IRQ for tight timestamps / wake support */
 #define EC_SYNC_IRQ	0
 /* eSPI virtual wire reporting */