diff options
| author | Gaggery Tsai <gaggery.tsai@intel.com> | 2022-04-25 22:10:32 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-27 20:16:04 +0000 |
| commit | 2f4246ab0c3948d791c50aa2450f522e2b009e5b (patch) | |
| tree | ea4a0cc4c3e31927b5e5584eacb57271b1b3153d /src/mainboard/google | |
| parent | 248916ad5713da5a2a0e7a9a06792be389d5223a (diff) | |
mb/google/brya/var/vell: Enable TBT PCIe root port 3
This patch enables TBT PCIe root port 3.
BUG=b:230464233
TEST=emerge-brya coreboot chromeos-bootimage and $lspci -t and
ensure 07.3 is in the list.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I118facd45f54c8ed2843a85c0aa61b6571077a5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/overridetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index cd813bf6f8..aa8350fdb9 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -69,6 +69,7 @@ chip soc/intel/alderlake }" register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)" # USB2_C3 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" + register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC3)" register "sagv" = "SaGv_Enabled" # FIVR RFI Spread Spectrum 6% @@ -171,6 +172,7 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end + device ref tbt_pcie_rp3 on end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" |