diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-04-02 10:42:47 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-19 13:09:44 +0000 |
| commit | 2c4b42655765fc4a1ef431c7ca276032bd14e1f9 (patch) | |
| tree | b4bb2680d3d141982550ffaf04fb3916a6e47209 /src/mainboard/google | |
| parent | 5215f2ffcb04d2c5782f46807d41e2ffb361ed2b (diff) | |
mb/google/brya: Disable PCH USB2 phy power gating for felwinter
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for felwinter board. Please refer Intel doc#723158 for
more information.
BUG=b:221461379, b:226020977
TEST=Verify the build for felwinter board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/brya/variants/felwinter/overridetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index a89ad95243..d2ecf4a5b0 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -44,6 +44,10 @@ chip soc/intel/alderlake [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" + # As per Intel Advisory doc#723158, the change is required to prevent possible + # display flickering issue. + register "usb2_phy_sus_pg_disable" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |