skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPI

Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all
skylake boards to use common gpio driver. Common gpio code
defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for
skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This
resulted in Linux kernel failing to configure all GPIO IRQs since the
ownership was not set correctly. (Observed error in dmesg: "genirq:
Setting trigger mode 3 for irq 201
failed (intel_gpio_irq_type+0x0/0x110)")

This change fixes the above issue by replacing all uses of PAD_CFG_GPI
in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.

BUG=b:67507004
TEST=Verified on soraka that the genirq error is no longer observed in
dmesg. Also, cat /proc/interrupts has the interrupts configured
correctly.

Change-Id: I7dab302f372e56864432100a56462b92d43060ee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

7 files changed, 130 insertions, 101 deletions

diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h
index 6f30e1e849..76b2d09cc8 100644
--- a/src/mainboard/google/chell/gpio.h
+++ b/src/mainboard/google/chell/gpio.h
@@ -106,23 +106,23 @@ static const struct pad_config gpio_table[] = {
 /* GSPI1_CLK */		PAD_CFG_NC(GPP_B20),
 /* GSPI1_MISO */	PAD_CFG_NC(GPP_B21),
 /* GSPI1_MOSI */	PAD_CFG_GPO(GPP_B22, 0, DEEP),
-/* SM1ALERT# */		PAD_CFG_GPI(GPP_B23, NONE, DEEP), /* UNUSED */
+/* SM1ALERT# */		PAD_CFG_GPI_GPIO_DRIVER(GPP_B23, NONE, DEEP), /* UNUSED */
 /* SMBCLK */		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */
 /* SMBDATA */		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */
 /* SMBALERT# */		PAD_CFG_GPO(GPP_C2, 0, DEEP),
-/* SML0CLK */		PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* UNUSED */
-/* SML0DATA */		PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* UNUSED */
-/* SML0ALERT# */	PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* UNUSED */
-/* SM1CLK */		PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
-/* SM1DATA */		PAD_CFG_GPI(GPP_C7, NONE, DEEP), /* UNUSED */
+/* SML0CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* UNUSED */
+/* SML0DATA */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* UNUSED */
+/* SML0ALERT# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C5, NONE, DEEP), /* UNUSED */
+/* SM1CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
+/* SM1DATA */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), /* UNUSED */
 /* UART0_RXD */		PAD_CFG_NC(GPP_C8),
 /* UART0_TXD */		PAD_CFG_NC(GPP_C9),
 /* UART0_RTS# */	PAD_CFG_NC(GPP_C10),
 /* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
-/* UART1_RXD */		PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
-/* UART1_TXD */		PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
-/* UART1_RTS# */	PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
-/* UART1_CTS# */	PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
+/* UART1_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
+/* UART1_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
+/* UART1_RTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
+/* UART1_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
 /* I2C0_SDA */		PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */
 /* I2C0_SCL */		PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */
 /* I2C1_SDA */		PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TRACKPAD */
@@ -130,7 +130,7 @@ static const struct pad_config gpio_table[] = {
 /* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
 /* UART2_RTS# */	PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */
-/* UART2_CTS# */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
 /* SPI1_CS# */		PAD_CFG_GPO(GPP_D0, 0, DEEP),
 /* SPI1_CLK */		PAD_CFG_GPO(GPP_D1, 0, DEEP),
 /* SPI1_MISO */		PAD_CFG_GPO(GPP_D2, 0, DEEP),
@@ -184,10 +184,10 @@ static const struct pad_config gpio_table[] = {
  * together with i2s0 signals. For default behavior of i2s make these
  * gpio inupts.
  */
-/* I2S2_SCLK */		PAD_CFG_GPI(GPP_F0, NONE, DEEP),
-/* I2S2_SFRM */		PAD_CFG_GPI(GPP_F1, NONE, DEEP),
-/* I2S2_TXD */		PAD_CFG_GPI(GPP_F2, NONE, DEEP),
-/* I2S2_RXD */		PAD_CFG_GPI(GPP_F3, NONE, DEEP),
+/* I2S2_SCLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
+/* I2S2_SFRM */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
+/* I2S2_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
+/* I2S2_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
 /* I2C2_SDA */		PAD_CFG_NC(GPP_F4),
 /* I2C2_SCL */		PAD_CFG_NC(GPP_F5),
 /* I2C3_SDA */		PAD_CFG_NC(GPP_F6),
@@ -234,7 +234,7 @@ static const struct pad_config gpio_table[] = {
 static const struct pad_config early_gpio_table[] = {
 /* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
 /* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
-/* UART2_CTS# */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
 };
 
 #endif
diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h
index b8850690ff..b9b37a07a2 100644
--- a/src/mainboard/google/eve/gpio.h
+++ b/src/mainboard/google/eve/gpio.h
@@ -100,16 +100,21 @@ static const struct pad_config gpio_table[] = {
 /* SML0CLK */		PAD_CFG_NC(GPP_C3),
 /* SML0DATA */		PAD_CFG_NC(GPP_C4),
 /* SML0ALERT# */	PAD_CFG_NC(GPP_C5),
-/* SM1CLK */		PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
+/* SM1CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU,
+						DEEP), /* EC_IN_RW */
 /* SM1DATA */		PAD_CFG_NC(GPP_C7),
 /* UART0_RXD */		PAD_CFG_NC(GPP_C8),
 /* UART0_TXD */		PAD_CFG_NC(GPP_C9),
 /* UART0_RTS# */	PAD_CFG_NC(GPP_C10),
 /* UART0_CTS# */	PAD_CFG_NC(GPP_C11),
-/* UART1_RXD */		PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
-/* UART1_TXD */		PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
-/* UART1_RTS# */	PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
-/* UART1_CTS# */	PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
+/* UART1_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,
+						DEEP), /* MEM_CONFIG[0] */
+/* UART1_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,
+						DEEP), /* MEM_CONFIG[1] */
+/* UART1_RTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,
+						DEEP), /* MEM_CONFIG[2] */
+/* UART1_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,
+						DEEP), /* MEM_CONFIG[3] */
 /* I2C0_SDA */		PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */
 /* I2C0_SCL */		PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */
 /* I2C1_SDA */		PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TPM */
@@ -117,10 +122,12 @@ static const struct pad_config gpio_table[] = {
 /* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
 /* UART2_RTS# */	PAD_CFG_GPO(GPP_C22, 0, DEEP), /* EN_PP3300_DX_TOUCHSCREEN */
-/* UART2_CTS# */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU,
+						DEEP), /* PCH_WP */
 
 /* SPI1_CS# */		PAD_CFG_GPO(GPP_D0, 0, DEEP), /* TOUCHPAD_BOOT */
-/* SPI1_CLK */		PAD_CFG_GPI(GPP_D1, NONE, DEEP), /* TOUCHPAD_RESET */
+/* SPI1_CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_D1, NONE,
+						DEEP), /* TOUCHPAD_RESET */
 /* SPI1_MISO */		PAD_CFG_NC(GPP_D2),
 /* SPI1_MOSI */		PAD_CFG_NC(GPP_D3),
 /* FASHTRIG */		PAD_CFG_NC(GPP_D4),
@@ -155,7 +162,8 @@ static const struct pad_config gpio_table[] = {
 /* SATALED# */		PAD_CFG_NC(GPP_E8),
 /* USB2_OCO# */		PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_C0_OC_ODL */
 /* USB2_OC1# */		PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_C1_OC_ODL */
-/* USB2_OC2# */		PAD_CFG_GPI(GPP_E11, NONE, DEEP), /* TOUCHSCREEN_STOP_L */
+/* USB2_OC2# */		PAD_CFG_GPI_GPIO_DRIVER(GPP_E11, NONE,
+						DEEP), /* TOUCHSCREEN_STOP_L */
 /* USB2_OC3# */		PAD_CFG_NC(GPP_E12),
 /* DDPB_HPD0 */		PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1), /* USB_C0_DP_HPD */
 /* DDPC_HPD1 */		PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1), /* USB_C1_DP_HPD */
@@ -170,14 +178,16 @@ static const struct pad_config gpio_table[] = {
 /* DDPD_CTRLDATA */	PAD_CFG_NC(GPP_E23),
 
 /* The next 4 pads are for bit banging the amplifiers, default to I2S */
-/* I2S2_SCLK */		PAD_CFG_GPI(GPP_F0, NONE, DEEP),
-/* I2S2_SFRM */		PAD_CFG_GPI(GPP_F1, NONE, DEEP),
-/* I2S2_TXD */		PAD_CFG_GPI(GPP_F2, NONE, DEEP),
-/* I2S2_RXD */		PAD_CFG_GPI(GPP_F3, NONE, DEEP),
+/* I2S2_SCLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
+/* I2S2_SFRM */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
+/* I2S2_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
+/* I2S2_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
 /* I2C2_SDA */		PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* TOUCHPAD */
 /* I2C2_SCL */		PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* TOUCHPAD */
-/* I2C3_SDA */		PAD_CFG_GPI(GPP_F6, NONE, DEEP), /* DISPLAY is master */
-/* I2C3_SCL */		PAD_CFG_GPI(GPP_F7, NONE, DEEP), /* DISPLAY is master */
+/* I2C3_SDA */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F6, NONE,
+						DEEP), /* DISPLAY is master */
+/* I2C3_SCL */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F7, NONE,
+						DEEP), /* DISPLAY is master */
 /* I2C4_SDA */		PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */
 /* I2C4_SCL */		PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */
 /* I2C5_SDA */		PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */
@@ -222,7 +232,8 @@ static const struct pad_config gpio_table[] = {
 static const struct pad_config early_gpio_table[] = {
 /* I2C1_SDA */		PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TPM */
 /* I2C1_SCL */		PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */
-/* UART2_CTS# */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU,
+						DEEP), /* PCH_WP */
 /* SATAXPCI0 */		PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */
 
 /* Ensure UART pins are in native mode for H1 */
diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h
index ae952862e8..330ba4eee2 100644
--- a/src/mainboard/google/fizz/gpio.h
+++ b/src/mainboard/google/fizz/gpio.h
@@ -49,13 +49,14 @@ static const struct pad_config gpio_table[] = {
 /* CLKOUT_LPC1 */	PAD_CFG_NC(GPP_A10), /* TP188 */
 /* PME# */		PAD_CFG_NC(GPP_A11), /* TP149 */
 /* BM_BUSY# */		PAD_CFG_NC(GPP_A12),
-/* SUSWARN# */		PAD_CFG_GPI(GPP_A13, NONE, DEEP), /* eSPI mode */
+/* SUSWARN# */		PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE,
+						DEEP), /* eSPI mode */
 /* ESPI_RESET# */
 /* SUSACK# */		PAD_CFG_NC(GPP_A15), /* TP150 */
 /* SD_1P8_SEL */	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
 /* SD_PWR_EN# */	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
 /* ISH_GP0 */		PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */
-/* ISH_GP1 */		PAD_CFG_GPI(GPP_A19, NONE, DEEP), /* HDPO */
+/* ISH_GP1 */		PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */
 /* ISH_GP2 */		PAD_CFG_NC(GPP_A20),
 /* ISH_GP3 */		PAD_CFG_NC(GPP_A21),
 /* ISH_GP4 */		PAD_CFG_NC(GPP_A22),
@@ -96,8 +97,10 @@ static const struct pad_config gpio_table[] = {
 /* GSPI0_MOSI */	PAD_CFG_NC(GPP_B18),
 #endif
 /* GSPI1_CS# */		PAD_CFG_NC(GPP_B19), /* TP111 */
-/* GSPI1_CLK */		PAD_CFG_GPI(GPP_B20, 20K_PU, DEEP), /* VR_DISABLE_L */
-/* GSPI1_MISO */	PAD_CFG_GPI(GPP_B21, 20K_PU, DEEP), /* HWA_TRST_N */
+/* GSPI1_CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU,
+						DEEP), /* VR_DISABLE_L */
+/* GSPI1_MISO */	PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU,
+						DEEP), /* HWA_TRST_N */
 /* GSPI1_MOSI */	PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */
 /* SML1ALERT# */		PAD_CFG_NC(GPP_B23), /* TP141 */
 
@@ -107,16 +110,25 @@ static const struct pad_config gpio_table[] = {
 /* SML0CLK */		PAD_CFG_NC(GPP_C3),
 /* SML0DATA */		PAD_CFG_NC(GPP_C4),
 /* SML0ALERT# */	PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
-/* SM1CLK */		PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
+/* SM1CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU,
+						DEEP), /* EC_IN_RW */
 /* SM1DATA */		PAD_CFG_NC(GPP_C7), /* TP310 */
-/* UART0_RXD */		PAD_CFG_GPI(GPP_C8, 20K_PU, DEEP), /* GPIO1 */
-/* UART0_TXD */		PAD_CFG_GPI(GPP_C9, 20K_PU, DEEP), /* GPIO2 */
-/* UART0_RTS# */	PAD_CFG_GPI(GPP_C10, 20K_PU, DEEP), /* GPIO3 */
-/* UART0_CTS# */	PAD_CFG_GPI(GPP_C11, 20K_PU, DEEP), /* GPIO4 */
-/* UART1_RXD */		PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* SKU_ID0 */
-/* UART1_TXD */		PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* SKU_ID1 */
-/* UART1_RTS# */	PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* SKU_ID2 */
-/* UART1_CTS# */	PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* SKU_ID3 */
+/* UART0_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU,
+							DEEP), /* GPIO1 */
+/* UART0_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU,
+							DEEP), /* GPIO2 */
+/* UART0_RTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, 20K_PU,
+						DEEP), /* GPIO3 */
+/* UART0_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU,
+						DEEP), /* GPIO4 */
+/* UART1_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,
+							DEEP), /* SKU_ID0 */
+/* UART1_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,
+							DEEP), /* SKU_ID1 */
+/* UART1_RTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,
+						DEEP), /* SKU_ID2 */
+/* UART1_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,
+						DEEP), /* SKU_ID3 */
 /* I2C0_SDA */		PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 /* I2C0_SCL */		PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 #if IS_ENABLED(CONFIG_FIZZ_USE_I2C_TPM)
@@ -131,7 +143,7 @@ static const struct pad_config gpio_table[] = {
 /* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
 /* UART2_RTS# */	PAD_CFG_NC(GPP_C22), /* TP309 */
-/* UART2_CTS# */	PAD_CFG_GPI(GPP_C23, NONE,
+/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,
 				    DEEP), /* SCREW_SPI_WP_STATUS */
 
 /* SPI1_CS# */		PAD_CFG_NC(GPP_D0), /* TP259 */
@@ -270,7 +282,7 @@ static const struct pad_config early_gpio_table[] = {
 /* Ensure UART pins are in native mode for H1. */
 /* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
-/* UART2_CTS# */	PAD_CFG_GPI(GPP_C23, NONE,
+/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,
 				    DEEP), /* SCREW_SPI_WP_STATUS */
 };
 
diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h
index 8e5e16228b..acd0eada1b 100644
--- a/src/mainboard/google/glados/gpio.h
+++ b/src/mainboard/google/glados/gpio.h
@@ -107,19 +107,24 @@ static const struct pad_config gpio_table[] = {
 /* SMBCLK */		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */
 /* SMBDATA */		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */
 /* SMBALERT# */		/* GPP_C2 */
-/* SML0CLK */		PAD_CFG_GPI(GPP_C3, NONE, DEEP),
-/* SML0DATA */		PAD_CFG_GPI(GPP_C4, NONE, DEEP),
+/* SML0CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP),
+/* SML0DATA */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP),
 /* SML0ALERT# */	PAD_CFG_GPO(GPP_C5, 0, DEEP),
-/* SM1CLK */		PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
-/* SM1DATA */		PAD_CFG_GPI(GPP_C7, NONE, DEEP),
+/* SM1CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU,
+						DEEP), /* EC_IN_RW */
+/* SM1DATA */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP),
 /* UART0_RXD */		/* GPP_C8 */
 /* UART0_TXD */		/* GPP_C9 */
 /* UART0_RTS# */	/* GPP_C10 */
 /* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
-/* UART1_RXD */		PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
-/* UART1_TXD */		PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
-/* UART1_RTS# */	PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
-/* UART1_CTS# */	PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
+/* UART1_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,
+						DEEP), /* MEM_CONFIG[0] */
+/* UART1_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,
+						DEEP), /* MEM_CONFIG[1] */
+/* UART1_RTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE,
+						DEEP), /* MEM_CONFIG[2] */
+/* UART1_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,
+						DEEP), /* MEM_CONFIG[3] */
 /* I2C0_SDA */		PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */
 /* I2C0_SCL */		PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */
 /* I2C1_SDA */		PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TRACKPAD */
@@ -127,7 +132,8 @@ static const struct pad_config gpio_table[] = {
 /* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
 /* UART2_RTS# */	PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */
-/* UART2_CTS# */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU,
+						DEEP), /* PCH_WP */
 			/* GPP_D0 */
 			/* GPP_D1 */
 			/* GPP_D2 */
@@ -181,10 +187,10 @@ static const struct pad_config gpio_table[] = {
  * together with i2s0 signals. For default behavior of i2s make these
  * gpio inupts.
  */
-/* I2S2_SCLK */		PAD_CFG_GPI(GPP_F0, NONE, DEEP),
-/* I2S2_SFRM */		PAD_CFG_GPI(GPP_F1, NONE, DEEP),
-/* I2S2_TXD */		PAD_CFG_GPI(GPP_F2, NONE, DEEP),
-/* I2S2_RXD */		PAD_CFG_GPI(GPP_F3, NONE, DEEP),
+/* I2S2_SCLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
+/* I2S2_SFRM */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
+/* I2S2_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
+/* I2S2_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
 /* I2C2_SDA */		/* GPP_F4 */
 /* I2C2_SCL */		/* GPP_F5 */
 /* I2C3_SDA */		/* GPP_F6 */
diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h
index 40960a7299..77151a4b9e 100644
--- a/src/mainboard/google/lars/gpio.h
+++ b/src/mainboard/google/lars/gpio.h
@@ -94,10 +94,10 @@ static const struct pad_config gpio_table[] = {
 /* MPHY_EXT_PWR_GATE */	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
 /* PM_SLP_S0 */		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 /* PCH_PLT_RST */	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-/* GPP_B_14_SPKR */	PAD_CFG_GPI(GPP_B14, NONE, DEEP),
+/* GPP_B_14_SPKR */	PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP),
 /* GSPI0_CS# */		/* GPP_B15 */
 /* WLAN_PCIE_WAKE */	PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
-/* SSD_PCIE_WAKE */	PAD_CFG_GPI(GPP_B17, NONE, DEEP),
+/* SSD_PCIE_WAKE */	PAD_CFG_GPI_GPIO_DRIVER(GPP_B17, NONE, DEEP),
 /* GSPI0_MOSI */	/* GPP_B18 */
 /* CCODEC_SPI_CS */	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
 /* CODEC_SPI_CLK */	PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
@@ -108,18 +108,18 @@ static const struct pad_config gpio_table[] = {
 /* SMB_DATA */		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 /* SMBALERT# */		PAD_CFG_GPO(GPP_C2, 0, DEEP),
 /* M2_WWAN_PWREN */	PAD_CFG_GPO(GPP_C3, 0, DEEP),
-/* SML0DATA */		PAD_CFG_GPI(GPP_C4, NONE, DEEP),
+/* SML0DATA */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP),
 /* SML0ALERT# */	PAD_CFG_GPO(GPP_C5, 0, DEEP),
-/* EC_IN_RW */		PAD_CFG_GPI(GPP_C6, NONE, DEEP),
+/* EC_IN_RW */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP),
 /* USB_CTL */		PAD_CFG_GPO(GPP_C7, 1, DEEP),
 /* UART0_RXD */		/* GPP_C8 */
 /* UART0_TXD */		/* GPP_C9 */
 /* NFC_RST* */		PAD_CFG_GPO(GPP_C10, 0, DEEP),
 /* EN_PP3300_KEPLER */	PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP),
-/* PCH_MEM_CFG0 */	PAD_CFG_GPI(GPP_C12, NONE, DEEP),
-/* PCH_MEM_CFG1 */	PAD_CFG_GPI(GPP_C13, NONE, DEEP),
-/* PCH_MEM_CFG2 */	PAD_CFG_GPI(GPP_C14, NONE, DEEP),
-/* PCH_MEM_CFG3 */	PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+/* PCH_MEM_CFG0 */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
+/* PCH_MEM_CFG1 */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),
+/* PCH_MEM_CFG2 */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),
+/* PCH_MEM_CFG3 */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),
 /* I2C0_SDA */		PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
 /* I2C0_SCL */		PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
 /* I2C1_SDA */		PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
@@ -127,7 +127,7 @@ static const struct pad_config gpio_table[] = {
 /* GD_UART2_RXD */	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 /* GD_UART2_TXD */	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 /* TCH_PNL_PWREN */	PAD_CFG_GPO(GPP_C22, 1, DEEP),
-/* SPI_WP_STATUS */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+/* SPI_WP_STATUS */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
 /* ITCH_SPI_CS */	/* GPP_D0 */
 /* ITCH_SPI_CLK */	/* GPP_D1 */
 /* ITCH_SPI_MISO_1 */	/* GPP_D2 */
@@ -174,12 +174,12 @@ static const struct pad_config gpio_table[] = {
 /* DDPB_CTRLDATA */	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
 /* DDPC_CTRLCLK */	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
 /* DDPC_CTRLDATA */	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
-/* DDPD_CTRLCLK */	PAD_CFG_GPI(GPP_E22, NONE, DEEP),
+/* DDPD_CTRLCLK */	PAD_CFG_GPI_GPIO_DRIVER(GPP_E22, NONE, DEEP),
 /* TCH_PNL_RST */	PAD_CFG_GPO(GPP_E23, 1, DEEP),
-/* I2S2_SCLK */		PAD_CFG_GPI(GPP_F0, NONE, DEEP),
-/* I2S2_SFRM */		PAD_CFG_GPI(GPP_F1, NONE, DEEP),
-/* I2S2_TXD */		PAD_CFG_GPI(GPP_F2, NONE, DEEP),
-/* I2S2_RXD */		PAD_CFG_GPI(GPP_F3, NONE, DEEP),
+/* I2S2_SCLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
+/* I2S2_SFRM */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
+/* I2S2_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
+/* I2S2_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
 /* I2C2_SDA */		PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
 /* I2C2_SCL */		PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
 /* I2C3_SDA */		/* GPP_F6 */
@@ -226,7 +226,7 @@ static const struct pad_config gpio_table[] = {
 static const struct pad_config early_gpio_table[] = {
 /* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
 /* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
-/* SPI_WP_STATUS */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+/* SPI_WP_STATUS */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
 };
 
 #endif
diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c
index e74e4afcf6..90a161126d 100644
--- a/src/mainboard/google/poppy/variants/baseboard/gpio.c
+++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c
@@ -135,7 +135,7 @@ static const struct pad_config gpio_table[] = {
 	/* C5  : SML0ALERT# ==> NC */
 	PAD_CFG_NC(GPP_C5),
 	/* C6  : SM1CLK ==> EC_IN_RW_OD */
-	PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),
 	/* C7  : SM1DATA ==> NC */
 	PAD_CFG_NC(GPP_C7),
 	/* C8  : UART0_RXD ==> FP_INT */
@@ -147,13 +147,13 @@ static const struct pad_config gpio_table[] = {
 	/* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */
 	PAD_CFG_GPO(GPP_C11, 0, DEEP),
 	/* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
-	PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
 	/* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */
-	PAD_CFG_GPI(GPP_C13, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),
 	/* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */
-	PAD_CFG_GPI(GPP_C14, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),
 	/* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */
-	PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),
 	/* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 	/* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */
@@ -176,14 +176,14 @@ static const struct pad_config gpio_table[] = {
 	/* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */
 	PAD_CFG_GPO(GPP_C22, 0, DEEP),
 	/* C23 : UART2_CTS# ==> PCH_WP */
-	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
 
 	/* D0  : SPI1_CS# ==> NC */
 	PAD_CFG_NC(GPP_D0),
 	/* D1  : SPI1_CLK ==> PEN_IRQ_L */
 	PAD_CFG_GPI_APIC(GPP_D1, NONE, PLTRST),
 	/* D2  : SPI1_MISO ==> PEN_PDCT_L */
-	PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_D2, NONE, DEEP),
 	/* D3  : SPI1_MOSI ==> NC */
 	PAD_CFG_NC(GPP_D3),
 	/* D4  : FASHTRIG ==> NC */
@@ -197,7 +197,7 @@ static const struct pad_config gpio_table[] = {
 	/* D8  : ISH_I2C1_SCL ==> NC */
 	PAD_CFG_NC(GPP_D8),
 	/* D9  : ISH_SPI_CS# ==> HP_IRQ_GPIO */
-	PAD_CFG_GPI(GPP_D9, NONE, PLTRST),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST),
 	/* D10 : ISH_SPI_CLK ==> SPKR_RST_L */
 	PAD_CFG_GPO(GPP_D10, 1, DEEP),
 	/* D11 : ISH_SPI_MISO ==> SPKR_INT_L */
@@ -258,7 +258,7 @@ static const struct pad_config gpio_table[] = {
 	/* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */
 	PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),
 	/* E15 : DDPD_HPD2 ==> SD_CD# */
-	PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP),
 	/* E16 : DDPE_HPD3 ==> NC(TP244) */
 	PAD_CFG_NC(GPP_E16),
 	/* E17 : EDP_HPD */
@@ -278,13 +278,13 @@ static const struct pad_config gpio_table[] = {
 
 	/* The next 4 pads are for bit banging the amplifiers, default to I2S */
 	/* F0  : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */
-	PAD_CFG_GPI(GPP_F0, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
 	/* F1  : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */
-	PAD_CFG_GPI(GPP_F1, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
 	/* F2  : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */
-	PAD_CFG_GPI(GPP_F2, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
 	/* F3  : I2S2_RXD */
-	PAD_CFG_GPI(GPP_F3, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
 	/* F4  : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */
 	PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
 	/* F5  : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */
@@ -396,7 +396,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 
 	/* C23 : UART2_CTS# ==> PCH_WP */
-	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
 
 	/* E0  : SATAXPCI0 ==> H1_PCH_INT_ODL */
 	PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c
index cd1258db95..92f866f399 100644
--- a/src/mainboard/google/poppy/variants/soraka/gpio.c
+++ b/src/mainboard/google/poppy/variants/soraka/gpio.c
@@ -133,7 +133,7 @@ static const struct pad_config gpio_table[] = {
 	/* C5  : SML0ALERT# ==> NC */
 	PAD_CFG_NC(GPP_C5),
 	/* C6  : SM1CLK ==> EC_IN_RW_OD */
-	PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),
 	/* C7  : SM1DATA ==> NC */
 	PAD_CFG_NC(GPP_C7),
 	/* C8  : UART0_RXD ==> FP_INT */
@@ -145,13 +145,13 @@ static const struct pad_config gpio_table[] = {
 	/* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */
 	PAD_CFG_GPO(GPP_C11, 0, DEEP),
 	/* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
-	PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
 	/* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */
-	PAD_CFG_GPI(GPP_C13, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),
 	/* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */
-	PAD_CFG_GPI(GPP_C14, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),
 	/* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */
-	PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),
 	/* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */
 	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 	/* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */
@@ -174,7 +174,7 @@ static const struct pad_config gpio_table[] = {
 	/* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */
 	PAD_CFG_GPO(GPP_C22, 0, DEEP),
 	/* C23 : UART2_CTS# ==> PCH_WP */
-	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
 
 	/* D0  : SPI1_CS# ==> NC */
 	PAD_CFG_NC(GPP_D0),
@@ -195,7 +195,7 @@ static const struct pad_config gpio_table[] = {
 	/* D8  : ISH_I2C1_SCL ==> NC */
 	PAD_CFG_NC(GPP_D8),
 	/* D9  : ISH_SPI_CS# ==> HP_IRQ_GPIO */
-	PAD_CFG_GPI(GPP_D9, NONE, PLTRST),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST),
 	/* D10 : ISH_SPI_CLK ==> SPKR_RST_L */
 	PAD_CFG_GPO(GPP_D10, 1, DEEP),
 	/* D11 : ISH_SPI_MISO ==> SPKR_INT_L */
@@ -256,7 +256,7 @@ static const struct pad_config gpio_table[] = {
 	/* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */
 	PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),
 	/* E15 : DDPD_HPD2 ==> SD_CD# */
-	PAD_CFG_GPI(GPP_E15, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP),
 	/* E16 : DDPE_HPD3 ==> NC(TP244) */
 	PAD_CFG_NC(GPP_E16),
 	/* E17 : EDP_HPD */
@@ -276,13 +276,13 @@ static const struct pad_config gpio_table[] = {
 
 	/* The next 4 pads are for bit banging the amplifiers, default to I2S */
 	/* F0  : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */
-	PAD_CFG_GPI(GPP_F0, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
 	/* F1  : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */
-	PAD_CFG_GPI(GPP_F1, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
 	/* F2  : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */
-	PAD_CFG_GPI(GPP_F2, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
 	/* F3  : I2S2_RXD */
-	PAD_CFG_GPI(GPP_F3, NONE, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
 	/* F4  : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */
 	PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
 	/* F5  : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */
@@ -397,7 +397,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 
 	/* C23 : UART2_CTS# ==> PCH_WP */
-	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
 
 	/* E0  : SATAXPCI0 ==> H1_PCH_INT_ODL */
 	PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),