diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2017-05-26 15:55:04 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-05-31 01:26:27 +0200 |
| commit | 07a597feffa63bdc8212a323f0a71ecbdf229dab (patch) | |
| tree | ee6cd35e3a14d6d84e3c9d26139a099330138a18 /src/mainboard/google | |
| parent | f124b88cfbc990be0c34b0edc82b7ba870828f2e (diff) | |
mb/google/eve: Update thermal tuning parameters
Modify the DPTF configuration on Eve to relax the severe throttling that
is currently applied and allow performance testing to see better results.
BUG=b:35581264
TEST=performance tests show better results and thermal tests still pass.
Change-Id: I0838f4ec3026bc8bac814698043fa97cf6772cb4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/eve/acpi/dptf.asl | 24 | ||||
| -rw-r--r-- | src/mainboard/google/eve/devicetree.cb | 2 |
2 files changed, 13 insertions, 13 deletions
diff --git a/src/mainboard/google/eve/acpi/dptf.asl b/src/mainboard/google/eve/acpi/dptf.asl index eaacb46f43..8937ee95d0 100644 --- a/src/mainboard/google/eve/acpi/dptf.asl +++ b/src/mainboard/google/eve/acpi/dptf.asl @@ -29,12 +29,12 @@ #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "DRAM" -#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_PASSIVE 65 #define DPTF_TSR2_CRITICAL 75 #define DPTF_TSR3_SENSOR_ID 4 #define DPTF_TSR3_SENSOR_NAME "eMMC" -#define DPTF_TSR3_PASSIVE 55 +#define DPTF_TSR3_PASSIVE 65 #define DPTF_TSR3_CRITICAL 75 #undef DPTF_ENABLE_FAN_CONTROL @@ -56,19 +56,19 @@ Name (DTRT, Package () { Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, /* CPU Effect on Charger */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 50, 600, 0, 0, 0, 0 }, /* CPU Effect on DRAM */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, /* CPU Effect on eMMC */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 50, 600, 0, 0, 0, 0 }, /* Charger Throttle Effect on Charger (TSR1) */ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, /* Charger Throttle Effect on eMMC (TSR3) */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 200, 600, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, }) Name (MPPC, Package () @@ -77,15 +77,15 @@ Name (MPPC, Package () Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 2500, /* PowerLimitMinimum */ - 4500, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 250 /* StepSize */ + 7000, /* PowerLimitMaximum */ + 5000, /* TimeWindowMinimum */ + 5000, /* TimeWindowMaximum */ + 200 /* StepSize */ }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 7000, /* PowerLimitMinimum */ - 7000, /* PowerLimitMaximum */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 1000 /* StepSize */ diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index e255a7aa6d..81f235f06b 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -215,7 +215,7 @@ chip soc/intel/skylake register "speed_shift_enable" = "1" register "dptf_enable" = "1" - register "tdp_pl2_override" = "7" + register "tdp_pl2_override" = "15" register "tcc_offset" = "10" device cpu_cluster 0 on |