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authorAngel Pons <th3fanbus@gmail.com>2020-10-29 11:04:57 +0100
committerAngel Pons <th3fanbus@gmail.com>2021-01-24 12:02:43 +0000
commitd0b7a534ce798eff46a2de4857f48e65100c1572 (patch)
tree8a6685e5734ab35357f5f5c54b2edce083f31e34 /src/mainboard/google
parentb7fe4485751dc283babd80dd58cf0d23341fe9af (diff)
mb/google/jecht: Use Haswell CPU code
Change-Id: I6c106b152bb2824e000232d23c2991898b2c4475 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46946 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/jecht/Kconfig1
-rw-r--r--src/mainboard/google/jecht/devicetree.cb5
2 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig
index b04cc465fb..1ffc456ba7 100644
--- a/src/mainboard/google/jecht/Kconfig
+++ b/src/mainboard/google/jecht/Kconfig
@@ -1,5 +1,6 @@
config BOARD_GOOGLE_BASEBOARD_JECHT
def_bool n
+ select CPU_INTEL_HASWELL
select SOC_INTEL_BROADWELL
select BOARD_ROMSIZE_KB_8192
select SUPERIO_ITE_IT8772F
diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb
index 94fd8044c1..08b2c957c7 100644
--- a/src/mainboard/google/jecht/devicetree.cb
+++ b/src/mainboard/google/jecht/devicetree.cb
@@ -10,7 +10,10 @@ chip soc/intel/broadwell
register "gpu_dp_b_hotplug" = "0x06"
device cpu_cluster 0 on
- device lapic 0 on end
+ chip cpu/intel/haswell
+ device lapic 0 on end
+ device lapic 0xacac off end
+ end
end
device domain 0 on