diff options
| author | Furquan Shaikh <furquan@google.com> | 2014-09-22 14:58:05 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-28 08:44:56 +0100 |
| commit | ba167251e2d0722dc5a00c7e3bea08d2d4c3c078 (patch) | |
| tree | 6976fcfb927dd78580ab49796591c4f012f59ab2 /src/mainboard/google | |
| parent | 68a672c2c268295136e1ca186cab390494088490 (diff) | |
tegra132/rush/ryu: Use CLK_RST_REG instead of &clk_rst->...
BUG=chrome-os-partner:31821
BRANCH=None
TEST=Built and booted to kernel prompt on ryu. Rush compiled successfully.
Change-Id: I63ba55c53094c185d72dcb5c5d0d766461989806
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4a9aa565244bae5659e458ea90064eb5b803d574
Original-Change-Id: I5b00fbcb8e414c67563f1ad548f84c281898f939
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219392
Original-Reviewed-by: Tom Warren <twarren3959@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9100
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/rush/bootblock.c | 4 | ||||
| -rw-r--r-- | src/mainboard/google/rush_ryu/bootblock.c | 4 |
2 files changed, 2 insertions, 6 deletions
diff --git a/src/mainboard/google/rush/bootblock.c b/src/mainboard/google/rush/bootblock.c index 6b81a8b5b7..e84a25ef8b 100644 --- a/src/mainboard/google/rush/bootblock.c +++ b/src/mainboard/google/rush/bootblock.c @@ -31,8 +31,6 @@ #include "pmic.h" -static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; - static const struct pad_config uart_console_pads[] = { /* UARTA: tx and rx. */ PAD_CFG_SFIO(KB_ROW9, PINMUX_PULL_NONE, UA3), @@ -81,7 +79,7 @@ void bootblock_mainboard_early_init(void) static void set_clock_sources(void) { /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */ - writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta); + writel(PLLP << CLK_SOURCE_SHIFT, CLK_RST_REG(clk_src_uarta)); } void bootblock_mainboard_init(void) diff --git a/src/mainboard/google/rush_ryu/bootblock.c b/src/mainboard/google/rush_ryu/bootblock.c index 52a49a68da..9a1c68bb96 100644 --- a/src/mainboard/google/rush_ryu/bootblock.c +++ b/src/mainboard/google/rush_ryu/bootblock.c @@ -70,10 +70,8 @@ void bootblock_mainboard_early_init(void) static void set_clock_sources(void) { - struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; - /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */ - writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta); + writel(PLLP << CLK_SOURCE_SHIFT, CLK_RST_REG(clk_src_uarta)); } static const struct pad_config padcfgs[] = { |