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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-05-20 11:55:36 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-05-26 15:11:03 +0000
commitb30fe36734df3c48ec35438052ee8b28bf7a6a44 (patch)
tree3292f94f475a09678df0fc56f5450e6388c1fa2c /src/mainboard/google
parentb4d7116a740b2847ef112cc1954462dac0b4cf85 (diff)
soc/intel/tigerlake: Remove MIPI clock setting from devicetree
In Tiger Lake we have support for enabling MIPI clocks at runtime in ACPI. Hence remove setting pch_islclk from devcietree and chip.h. Also update functions which reference pch_isclk. BUG=b:148884060 Branch=None Test=build and boot volteer and verify camera functionality Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I6b3399172c43b4afa4267873ddd8ccf8d417ca16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41570 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 02060bdf45..c6a2e8b1a6 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -32,9 +32,6 @@ chip soc/intel/tigerlake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera
- # Enable Pch iSCLK
- register "pch_isclk" = "1"
-
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"