diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-07-31 17:23:32 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-28 09:53:01 +0000 |
| commit | b269f873b0a0d43911adc907a53bbebadc742b78 (patch) | |
| tree | 23e53691cef9dcfd19d63d8128e28638699aae97 /src/mainboard/google | |
| parent | 80346d04906261b258e1f7ea737a74beac08b11a (diff) | |
soc/intel/cannonlake: Update UPD from device switch
Some of the FSP silicon UPD entry can be updated base on device switch
in pci device tree, have both static config setting and device tree "on"
and "off" will be redundant.
BUG=N/A
TEST=Build and boot up fine with Whiskey Lake RVP platform.
Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27766
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/zoombini/variants/baseboard/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/zoombini/variants/meowth/devicetree.cb | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb index 479f28015a..f993ae95c3 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb @@ -21,9 +21,7 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "3" register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index bbff695b29..ef40ccce75 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -30,9 +30,7 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "1" # Intel Common SoC Config #+-------------------+---------------------------+ |