diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-05-18 12:41:28 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-20 09:12:36 +0000 |
| commit | af417b4143a689546b43ba106c2bd4a7d02053dc (patch) | |
| tree | 806f62272befec72529412b084067c72451749c5 /src/mainboard/google | |
| parent | 38c308515c4a983f361d287a3cbeec3ee36c52ae (diff) | |
mb/google/deltaur: Remove WLAN PCIE setting
Deltaur uses CNVi WLAN module, this setting is not required.
BUG=none
TEST=WiFi is functional in OS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idb23e271074c8d1e111c559695d4169af5e0d3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index b2062cbd07..7350319b22 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -51,11 +51,6 @@ chip soc/intel/tigerlake register "usb3_ports[2]" = "USB3_PORT_EMPTY" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - # PCIe root port 6 (WLAN), clock 1 - register "PcieRpEnable[5]" = "1" - register "PcieClkSrcUsage[1]" = "5" - register "PcieClkSrcClkReq[1]" = "1" - # PCIe root port 7 (Card Reader), clock 4 register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[4]" = "6" @@ -286,7 +281,7 @@ chip soc/intel/tigerlake device pci 1c.2 off end # PCIe Root Port #3 () device pci 1c.3 off end # PCIe Root Port #4 (WWAN) device pci 1c.4 on end # PCIe Root Port #5 (LTE) - device pci 1c.5 on end # PCIe Root Port #6 (WiFi) + device pci 1c.5 off end # PCIe Root Port #6 (WiFi) device pci 1c.6 on end # PCIe Root Port #7 (Card reader) device pci 1c.7 on chip drivers/net |