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authorAaron Durbin <adurbin@chromium.org>2017-01-20 14:03:50 -0600
committerAaron Durbin <adurbin@chromium.org>2017-01-21 21:45:05 +0100
commitaa6482e88e2f553ee841284e5b44672eee85d3ec (patch)
treeb76572b9300956367b27f32a5356886a879a4bc1 /src/mainboard/google
parent01bf599ea86abb360b0a57b892484dbb9c3ba387 (diff)
mainboard/google/reef: remove internal pullups on PP1800_S rail
The PP1800_S rail is turned off in S3. However, enabling internal pullups on the pins which are connected to PP1800_S results in leakage into the P1800_S rail. Fix this by disabling the internal pullups on PP1800_S rail pins. BUG=chrome-os-partner:61968 BRANCH=reef TEST=measured leakage on PP1800_S rail. Gone with this patch. Change-Id: I5ae92b31c1a633f59d425f4105b8db1c9c18c808 Signed-off-by: Aaron Duribn <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18189 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/reef/variants/baseboard/gpio.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c
index a764b466e1..390ef0f3da 100644
--- a/src/mainboard/google/reef/variants/baseboard/gpio.c
+++ b/src/mainboard/google/reef/variants/baseboard/gpio.c
@@ -58,8 +58,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */
PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */
PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */
- /* Card detect is active LOW. Pull up by 20K */
- PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */
+ /* Card detect is active LOW with external pull up. */
+ PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), /* SDCARD_CD_N */
PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */
/* CLK feedback, internal signal, needs 20K pull down */
PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */
@@ -288,7 +288,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* Board phase enforcement */
PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */
PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */
- PAD_CFG_GPI_APIC_LOW(GPIO_13, UP_20K, DEEP), /* PEN_INT_ODL */
+ PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP), /* PEN_INT_ODL */
PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */
PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */
PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */
@@ -299,7 +299,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */
PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, LEVEL), /* EC wake */
PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */
- PAD_CFG_GPI(GPIO_24, UP_20K, DEEP), /* PEN_PDCT_ODL */
+ PAD_CFG_GPI(GPIO_24, NONE, DEEP), /* PEN_PDCT_ODL */
PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_26, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_27, UP_20K, DEEP), /* unused */