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authorMichael Niewöhner <foss@mniewoehner.de>2019-10-22 23:05:06 +0200
committerNico Huber <nico.h@gmx.de>2019-11-04 19:25:02 +0000
commit7736bfc443a913a9cde46406bcfc38015ec71f47 (patch)
tree5b107551301bbaadc538b0c2ac7c52125462beb3 /src/mainboard/google
parente75a64f822931a5fbdd80f20c4d168a5c346e01a (diff)
soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig
The devicetree is not made for user-choosable options, thus introduce Kconfig options for both SGX and the corresponding PRMRR size. The PRMRR size Kconfig has been implemented as a maximum value. At runtime the final PRMRR size gets selected by checking the supported values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest to the chosen one. When "Maximum" is chosen, the highest possibly value from the MSR gets used. When a too strict limit is set, coreboot will die, printing an error message. Tested successfully on X11SSM-F Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
index bcad954885..d77633ddd7 100644
--- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
@@ -44,8 +44,6 @@ chip soc/intel/icelake
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
- register "PrmrrSize" = "0x10000000"
-
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"