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authorSathyanarayana Nujella <sathyanarayana.nujella@intel.com>2018-09-02 09:11:28 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-09-06 10:28:59 +0000
commit6f70d51facd3332f2fcc057fe0eed818d4d347c3 (patch)
tree3eb2b0c0a91429b255f3799a25a68216d3ef472c /src/mainboard/google
parent55597ff2799d0028179f0ce84a5c9cfec4971194 (diff)
mb/google/poppy/variants/nocturne: Enable DMIC CLK0/DATA0
DMIC's are now connected to DMIC_CLK0/DMIC_DATA0. So, enable the pins accordingly. BUG=b:113744731,b:111106010 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage' builds the image Change-Id: I48cace3c6099a2853fcb377c695a5e325094baf6 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/28433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/poppy/variants/nocturne/gpio.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c
index 782ce00670..08bb80162a 100644
--- a/src/mainboard/google/poppy/variants/nocturne/gpio.c
+++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c
@@ -199,10 +199,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
/* D18 : DMIC_DATA1 ==> PCH_DMIC_DATA */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
- /* D19 : DMIC_CLK0 ==> NC */
- PAD_CFG_NC(GPP_D19),
- /* D20 : DMIC_DATA0 ==> NC */
- PAD_CFG_NC(GPP_D20),
+ /* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */
+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+ /* D20 : DMIC_DATA0 ==> PCH_DMIC_DATA_IN */
+ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
/* D21 : SPI1_IO2 ==> NC */
PAD_CFG_NC(GPP_D21),
/* D22 : SPI1_IO3 ==> NC */