summaryrefslogtreecommitdiff
path: root/src/mainboard/google
diff options
context:
space:
mode:
authorT Michael Turney <mturney@codeaurora.org>2019-10-15 07:40:30 -0700
committerJulius Werner <jwerner@chromium.org>2019-11-01 01:16:35 +0000
commit626a53776b2915d7f27a8a97f9d84200b20f3079 (patch)
treec8e9cc83dd52210ae4e6d53d0bc47e6ef86645d0 /src/mainboard/google
parent09c3bfe826cf8ff30bab9ee073474674f1c9d565 (diff)
trogdor: Add mainboard gpio support
Change-Id: I06cdb8eaaf7f74b47e1d1283dcaa765674ceaa45 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36070 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/trogdor/Makefile.inc8
-rw-r--r--src/mainboard/google/trogdor/board.h30
-rw-r--r--src/mainboard/google/trogdor/boardid.c54
-rw-r--r--src/mainboard/google/trogdor/bootblock.c22
-rw-r--r--src/mainboard/google/trogdor/chromeos.c23
5 files changed, 136 insertions, 1 deletions
diff --git a/src/mainboard/google/trogdor/Makefile.inc b/src/mainboard/google/trogdor/Makefile.inc
index d4bf30509f..bda55be4fb 100644
--- a/src/mainboard/google/trogdor/Makefile.inc
+++ b/src/mainboard/google/trogdor/Makefile.inc
@@ -16,15 +16,23 @@
bootblock-y += memlayout.ld
bootblock-y += reset.c
+bootblock-y += boardid.c
+bootblock-y += chromeos.c
+bootblock-y += bootblock.c
verstage-y += memlayout.ld
verstage-y += reset.c
+verstage-y += boardid.c
+verstage-y += chromeos.c
romstage-y += memlayout.ld
romstage-y += romstage.c
romstage-y += reset.c
+romstage-y += boardid.c
+romstage-y += chromeos.c
ramstage-y += memlayout.ld
ramstage-y += mainboard.c
ramstage-y += reset.c
ramstage-y += chromeos.c
+ramstage-y += boardid.c
diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h
new file mode 100644
index 0000000000..f024e13646
--- /dev/null
+++ b/src/mainboard/google/trogdor/board.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_
+#define _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_
+
+#include <gpio.h>
+#include <soc/gpio.h>
+
+#define GPIO_EC_IN_RW GPIO(118)
+#define GPIO_AP_EC_INT GPIO(94)
+#define GPIO_AP_SUSPEND GPIO(20)
+#define GPIO_WP_STATE GPIO(42)
+#define GPIO_H1_AP_INT GPIO(21)
+
+void setup_chromeos_gpios(void);
+
+#endif /* _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ */
diff --git a/src/mainboard/google/trogdor/boardid.c b/src/mainboard/google/trogdor/boardid.c
new file mode 100644
index 0000000000..def3068d31
--- /dev/null
+++ b/src/mainboard/google/trogdor/boardid.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ * Copyright 2019 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <boardid.h>
+#include <gpio.h>
+
+uint32_t board_id(void)
+{
+ static uint32_t id = UNDEFINED_STRAPPING_ID;
+
+ const gpio_t pins[] = {[2] = GPIO(31), [1] = GPIO(93), [0] = GPIO(33)};
+
+ if (id == UNDEFINED_STRAPPING_ID)
+ id = gpio_base2_value(pins, ARRAY_SIZE(pins));
+
+ return id;
+}
+
+uint32_t ram_code(void)
+{
+ static uint32_t id = UNDEFINED_STRAPPING_ID;
+
+ const gpio_t pins[] = {[1] = GPIO(91), [0] = GPIO(29)};
+
+ if (id == UNDEFINED_STRAPPING_ID)
+ id = gpio_base2_value(pins, ARRAY_SIZE(pins));
+
+ return id;
+}
+
+uint32_t sku_id(void)
+{
+ static uint32_t id = UNDEFINED_STRAPPING_ID;
+
+ const gpio_t pins[] = {[1] = GPIO(90), [0] = GPIO(114)};
+
+ if (id == UNDEFINED_STRAPPING_ID)
+ id = gpio_base2_value(pins, ARRAY_SIZE(pins));
+
+ return id;
+}
diff --git a/src/mainboard/google/trogdor/bootblock.c b/src/mainboard/google/trogdor/bootblock.c
new file mode 100644
index 0000000000..c658093d07
--- /dev/null
+++ b/src/mainboard/google/trogdor/bootblock.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include "board.h"
+
+void bootblock_mainboard_init(void)
+{
+ setup_chromeos_gpios();
+}
diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c
index 1e8857db97..e84061352e 100644
--- a/src/mainboard/google/trogdor/chromeos.c
+++ b/src/mainboard/google/trogdor/chromeos.c
@@ -15,13 +15,34 @@
#include <boot/coreboot_tables.h>
#include <bootmode.h>
+#include "board.h"
int get_write_protect_state(void)
{
- return 0;
+ return !gpio_get(GPIO_WP_STATE);
+}
+
+void setup_chromeos_gpios(void)
+{
+ gpio_input_pullup(GPIO_EC_IN_RW);
+ gpio_input_pullup(GPIO_AP_EC_INT);
+ gpio_output(GPIO_AP_SUSPEND, 1);
+ gpio_input(GPIO_WP_STATE);
+ gpio_input_pullup(GPIO_H1_AP_INT);
}
void fill_lb_gpios(struct lb_gpios *gpios)
{
+ struct lb_gpio chromeos_gpios[] = {
+ {GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW),
+ "EC in RW"},
+ {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT),
+ "EC interrupt"},
+ {GPIO_WP_STATE.addr, ACTIVE_LOW, !get_write_protect_state(),
+ "write protect"},
+ {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT),
+ "TPM interrupt"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}