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authorMichael Niewöhner <foss@mniewoehner.de>2020-11-04 00:19:28 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-11-13 22:30:29 +0000
commit50a1072180f05c20ec13d521af6f8930ceabb2c3 (patch)
treec543067d8a7a77d49e6413a38774a71833c15b46 /src/mainboard/google
parent99b38a9c2fb3bbf52ad254bfcabc80c2d19d3185 (diff)
soc/intel/cnl: replace the remains of HeciEnabled by device state in dt
The option `HeciEnabled` was partly replaced by use of the device on/off state in the devicetree in commit 3de90d1. The option has been removed from the corresponding boards, so `HeciEnabled` is always 0 and ME always gets disabled during soc finalize, when `HECI_DISABLE_USING_SMM` is set. Replace the option in the finalize function by the same dt state check that sets the FSP option and drop the remaints of `HeciEnabled`. Devicetrees still having `HeciEnabled` have been adapted to keep the current behaviour. Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47195 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/hatch/variants/ambassador/overridetree.cb4
-rw-r--r--src/mainboard/google/hatch/variants/genesis/overridetree.cb4
2 files changed, 2 insertions, 6 deletions
diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb
index adb00e485f..835a8aae3a 100644
--- a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/ambassador/overridetree.cb
@@ -1,7 +1,4 @@
chip soc/intel/cannonlake
- # Enable heci communication
- register "HeciEnabled" = "1"
-
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
@@ -370,6 +367,7 @@ chip soc/intel/cannonlake
device i2c 4a on end
end
end # I2C #3, Realtek RTD2142.
+ device pci 16.0 on end # Management Engine Interface 1
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
diff --git a/src/mainboard/google/hatch/variants/genesis/overridetree.cb b/src/mainboard/google/hatch/variants/genesis/overridetree.cb
index adb00e485f..835a8aae3a 100644
--- a/src/mainboard/google/hatch/variants/genesis/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/genesis/overridetree.cb
@@ -1,7 +1,4 @@
chip soc/intel/cannonlake
- # Enable heci communication
- register "HeciEnabled" = "1"
-
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
@@ -370,6 +367,7 @@ chip soc/intel/cannonlake
device i2c 4a on end
end
end # I2C #3, Realtek RTD2142.
+ device pci 16.0 on end # Management Engine Interface 1
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""