diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2017-02-17 19:36:23 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-07 15:10:01 +0100 |
| commit | 2ea12e5ce05fb67b2eab30882c167551230b3a11 (patch) | |
| tree | 6553a5804c1d8414bf07a6ef3e571f6c82570efd /src/mainboard/google | |
| parent | 3329262ecaa2a21a88cad371c4d18e565a7bd542 (diff) | |
google/poppy: fix finger print sensor interrupt gpio configuration
Configure the right GPIOs for finger print sensor interrupt and reset
lines.
As per the schematics GPP_C8 is for sensor interrupt and GPP_C9
is for sensor reset.
Change-Id: Ib25c68ec2fe20b1302b6170d67ceab7e8cca1a83
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18389
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google')
| -rw-r--r-- | src/mainboard/google/poppy/gpio.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/poppy/gpio.h b/src/mainboard/google/poppy/gpio.h index b3849f1c00..72995a2e13 100644 --- a/src/mainboard/google/poppy/gpio.h +++ b/src/mainboard/google/poppy/gpio.h @@ -100,8 +100,8 @@ static const struct pad_config gpio_table[] = { /* SML0ALERT# */ PAD_CFG_NC(GPP_C5), /* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), +/* UART0_RXD */ PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST), /* FP_INT */ +/* UART0_TXD */ PAD_CFG_GPO(GPP_C9, 0, DEEP), /* FP_RST_ODL */ /* UART0_RTS# */ PAD_CFG_NC(GPP_C10), /* UART0_CTS# */ PAD_CFG_NC(GPP_C11), /* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ @@ -135,8 +135,8 @@ static const struct pad_config gpio_table[] = { /* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */ /* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12), -/* ISH_UART0_RXD */ PAD_CFG_GPI_APIC(GPP_D13, NONE, PLTRST), /* FP_INT */ -/* ISH_UART0_TXD */ PAD_CFG_GPO(GPP_D14, 0, DEEP), /* FP_RST_ODL */ +/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), /* ISH_UART0_RTS# */ PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST), /* MIC_IRQ_L */ /* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), /* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_CLK1 */ |