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authorJustin TerAvest <teravest@chromium.org>2018-01-29 20:11:00 -0700
committerAaron Durbin <adurbin@chromium.org>2018-01-31 21:06:28 +0000
commitf9bfe05bd1335bfaa4e93946a9a6eb9781576957 (patch)
treedb9fe0a89dd689a7cf32b7baf271df58c41ba724 /src/mainboard/google
parentb1204aab86a0b93671e2ee33ede41459254363c0 (diff)
mb/google/kahlee: Add grunt cr50 support
This commit adds an entry for H1/Cr50 into the devicetree for setting up ACPI entries for H1 communication. BUG=b:69250772 TEST=See probe messages in dmesg Change-Id: Id55ce3364ea4acdb62782758e5bcb2a167286cb9 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23514 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/kahlee/variants/grunt/devicetree.cb8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
index a5864b8be9..9665a78675 100644
--- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
@@ -82,6 +82,14 @@ chip soc/amd/stoneyridge
device pci 18.4 on end
device pci 18.5 on end
end #domain
+ device mmio 0xfedc3000 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "desc" = ""Cr50 TPM""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)"
+ device i2c 50 on end
+ end
+ end
device mmio 0xfedc4000 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""