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authorHung-Te Lin <hungte@chromium.org>2013-06-24 20:02:01 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 23:15:15 +0200
commitc357aed3d7954c87375ab5f7f6c0902a302adf09 (patch)
treee5aaad0e0b95d497fe84cffdf7db5c2dea407002 /src/mainboard/google
parente42030d23600990e95db2af1e9e1a366ff3d4ec7 (diff)
armv7/pit: Setup EC on SPI2.
The Embedded Controller (EC) for Pit is connected via SPI2, and needs to be configured before we can talk to it. Change-Id: I1f8e921b4616f15951f3e5fae1ecbf116de4ba90 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3707 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/pit/romstage.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c
index 41b64b2893..7ba66a4a35 100644
--- a/src/mainboard/google/pit/romstage.c
+++ b/src/mainboard/google/pit/romstage.c
@@ -122,6 +122,14 @@ static void setup_storage(void)
exynos_pinmux_sdmmc2();
}
+static void setup_ec(void)
+{
+ /* SPI2 (EC) is slower and needs to work in half-duplex mode with
+ * single byte bus width. */
+ clock_set_rate(PERIPH_ID_SPI2, 500000);
+ exynos_pinmux_spi2();
+}
+
static void setup_graphics(void)
{
exynos_pinmux_dphpd();
@@ -271,6 +279,7 @@ void main(void)
setup_storage();
setup_gpio();
setup_graphics();
+ setup_ec();
simple_spi_test();
/* Set SPI (primary CBFS media) clock to 50MHz. */