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authorChris Zhou <chris_zhou@compal.corp-partner.google.com>2019-02-19 15:56:15 +0800
committerDuncan Laurie <dlaurie@chromium.org>2019-02-20 03:14:26 +0000
commitba269fd77ee6582f3fac131e340803ec1ac1a81b (patch)
treea1eb8f4cec10259b1edda480fed5e3c8097b4728 /src/mainboard/google
parent34745f613f4a2970b2298bd76bfaf737229a4a3a (diff)
mb/google/sarien/variants/sarien: Adjust TP/TS I2C CLK to meet spec
After adjustment on Sarien EVT Touch Screen CLK (Elan): 389.7 KHz Touch Screen CLK (Melfas): 377.7 KHz Touch Pad CLK: 385 KHz BUG=b:122657195 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope with sarien. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: I53b60354e5a7a0ace8efb677775c0a9f8779061d Reviewed-on: https://review.coreboot.org/c/31476 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index bcd3c26abb..df22affcd9 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -157,12 +157,12 @@ chip soc/intel/cannonlake
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
- .rise_time_ns = 190,
- .fall_time_ns = 120,
+ .rise_time_ns = 100,
+ .fall_time_ns = 80,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
- .rise_time_ns = 52,
+ .rise_time_ns = 80,
.fall_time_ns = 110,
},
.i2c[4] = {