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authorStefan Reinauer <reinauer@chromium.org>2014-01-08 15:20:59 -0800
committerPatrick Georgi <patrick@georgi-clan.de>2014-07-12 20:16:54 +0200
commita0eeba47a16e5339f02a02ae85418bd9699975a4 (patch)
treed0dab644159c2f4ced97592e9ba423d607b89de0 /src/mainboard/google
parent1abeef60054f8e3d5b618a88c411d98591a5f4a3 (diff)
google/panther: Disable DEVSLP for SATA
Some SSD modules don't support DEVSLP correctly due to their firmware. Since the power savings are minimal, don't use DEVSLP to prevent potential problems. Some of the symptoms are that sometimes this causes USB devices to not work properly. BUG=chrome-os-partner:23186, BRANCH=panther TEST=Boot tested on Panther Change-Id: Iba3f721c73e0e760b6a9861ca23480ddb923df40 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181957 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5999 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/panther/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/panther/devicetree.cb b/src/mainboard/google/panther/devicetree.cb
index f461c589e2..9fbe8e62b3 100644
--- a/src/mainboard/google/panther/devicetree.cb
+++ b/src/mainboard/google/panther/devicetree.cb
@@ -55,6 +55,7 @@ chip northbridge/intel/haswell
register "ide_legacy_combined" = "0x0"
register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1"
+ register "sata_devslp_disable" = "0x1"
register "sio_acpi_mode" = "0"
register "sio_i2c0_voltage" = "0" # 3.3V